MPC8555ECPXAJD Freescale Semiconductor, MPC8555ECPXAJD Datasheet - Page 79

• Manufacturer Part Number: MPC8555ECPXAJD
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8555ECPXAJD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8555CDS - BOARD EVALUATION CDS FOR 8555CWH-PPC-8555N-VX - BOARD EVAL QUICCSTART MPC8555CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540CWH-PPC-8555N-VE - EVALUATION SYSTEM QUICC MPC8555E
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Figure 50
17.3
Due to large address and data buses, and high operating frequencies, the MPC8555E can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8555E system, and the
MPC8555E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each V
of the MPC8555E. These decoupling capacitors should receive their power from separate V
GV
Capacitors may be placed directly under the device using a standard escape pattern. Others may surround
the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
17.4
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OV
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
the MPC8555E.
17.5
The MPC8555E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I
To measure Z
or GND. Then, the value of each resistor is varied until the pad voltage is OV
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
Freescale Semiconductor
DD
, LV
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Connection Recommendations
Decoupling Recommendations
Output Buffer DC Impedance
shows the PLL power supply filter circuit.
DD
DD
, and GND power planes in the PCB, utilizing short traces to minimize inductance.
0
for the single-ended drivers, an external resistor is connected from the chip pad to OV
, OV
V
DD
DD
, GV
DD
Figure 50. PLL Power Supply Filter Circuit
, and LV
10 Ω
DD
2.2 µF
planes, to enable quick recharging of the smaller chip
GND
DD
Low ESL Surface Mount Capacitors
, GV
2
C).
2.2 µF
DD
DD
, or LV
, GV
AV
DD
DD
DD
DD
, LV
, OV
(or L2AV
as required. Unused active high
DD
DD
DD
, OV
, GV
DD
/2 (see
)
System Design Information
DD
DD
, and GND pins of
, and LV
Figure
DD
, OV
51). The
DD
pins
DD
DD
,
79