MPC8555ECPXAJD Freescale Semiconductor, MPC8555ECPXAJD Datasheet - Page 2

• Manufacturer Part Number: MPC8555ECPXAJD
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8555ECPXAJD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8555CDS - BOARD EVALUATION CDS FOR 8555CWH-PPC-8555N-VX - BOARD EVAL QUICCSTART MPC8555CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540CWH-PPC-8555N-VE - EVALUATION SYSTEM QUICC MPC8555E
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Overview
1
The following section provides a high-level overview of the MPC8555E features.
major functional units within the MPC8555E.
1.1
The following lists an overview of the MPC8555E feature set.
2
•
MIIs/RMIIs
UTOPIA
Overview
Embedded e500 Book E-compatible core
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit especially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
SDRAM
MPHY
TDMs
GPIO
IRQs
Key Features
32b
I/Os
DDR
DDR SDRAM Controller
Local Bus Controller
Interrupt Controller
Programmable
SCC/USB
I
2
C Controller
CPM
SMC
SMC
FCC
FCC
SCC
SCC
DUART
SPI
I
2
C
Generators
Parallel I/O
Baud Rate
I-Memory
Controller
Interrupt
DPRAM
Engine
Timers
Serial
RISC
CPM
ROM
DMA
Figure 1. MPC8555E Block Diagram
Coherency
Module
OCeaN
e500
Security
Engine
Core Complex
256-Kbyte
L2 Cache/
SRAM
Bus
64/32b PCI Controller
0/32b PCI Controller
10/100/1000 MAC
10/100/1000 MAC
DMA Controller
32-Kbyte L1
I Cache
Figure 1
e500 Core
Freescale Semiconductor
MII, GMII, TBI,
RTBI, RGMIIs
32-Kbyte L1
D Cache
shows the