MPC8555ECPXAJD Freescale Semiconductor, MPC8555ECPXAJD Datasheet - Page 55

• Manufacturer Part Number: MPC8555ECPXAJD
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8555ECPXAJD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8555CDS - BOARD EVALUATION CDS FOR 8555CWH-PPC-8555N-VX - BOARD EVAL QUICCSTART MPC8555CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540CWH-PPC-8555N-VE - EVALUATION SYSTEM QUICC MPC8555E
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

13.2
This section describes the general AC timing parameters of the PCI bus of the MPC8555E. Note that the
SYSCLK signal is used as the PCI input clock.
MHz.
Figure 16
Freescale Semiconductor
Clock to output valid
Output hold from Clock
Clock to output high impedance
Input setup to Clock
Input hold from Clock
REQ64 to HRESET
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications .
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
4. Input timings are measured at the pin.
5. The timing parameter t
6. The setup and hold time is with respect to the rising edge of HRESET.
7. The timing parameter t
8. The reset assertion timing requirement for HRESET is 100 μs.
9. Guaranteed by characterization.
10.Guaranteed by design.
(reference)(state)
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK
clock, t
the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
through the component pin is less than or equal to the leakage current specification.
system clock period must be kept within the minimum and maximum defined ranges. For values see
Specifications .
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
SYS
PCI AC Electrical Specifications
provides the AC test load for PCI.
, reference (K) going to the high (H) state or setup time. Also, t
PCI Clock can be PCI1_CLK or SYSCLK based on POR config input.
The input setup time does not meet the PCI specification.
for inputs and t
9
setup time
Parameter
SYS
PCRHFV
Output
indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
(first two letters of functional block)(reference)(state)(signal)(state)
Table 42. PCI AC Timing Specifications at 66 MHz
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
Figure 39. PCI AC Test Load
Z
0
= 50 Ω
Table 42
NOTE
NOTE
Symbol
t
t
t
t
t
t
PCKHOV
PCKHOX
t
t
PCKHOZ
PCRVRH
PCRHRX
PCRHFV
PCIVKH
PCIXKH
provides the PCI AC timing specifications at 66
1
PCRHFV
R
L
10 × t
= 50 Ω
Min
2.0
3.3
10
—
—
0
0
(first two letters of functional block)(signal)(state)
symbolizes PCI timing (PC) with respect to
SYS
for outputs. For example, t
OV
DD
Max
6.0
14
50
—
—
—
—
—
/2
Section 15,
clocks
clocks
Unit
ns
ns
ns
ns
ns
ns
PCIVKH
“Clocking.”
2, 3, 10
5, 6, 10
Notes
2, 4, 9
2, 4, 9
6, 10
7, 10
2, 3
2, 9
PCI
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