MPC8555ECPXAJD Freescale Semiconductor, MPC8555ECPXAJD Datasheet - Page 83

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MPC8555ECPXAJD

Manufacturer Part Number
MPC8555ECPXAJD
Description
IC MPU POWERQUICC III 783-FCPBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8555ECPXAJD

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
533MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
For Use With
MPC8555CDS - BOARD EVALUATION CDS FOR 8555CWH-PPC-8555N-VX - BOARD EVAL QUICCSTART MPC8555CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540CWH-PPC-8555N-VE - EVALUATION SYSTEM QUICC MPC8555E
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-

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17.8.1 Termination of Unused Signals
If the JTAG interface and COP header are not used, Freescale recommends the following connections:
Freescale Semiconductor
TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
the power-on reset flow. Freescale recommends that the COP header be designed into the system
as shown in
case a JTAG interface may need to be wired onto the system in future debug situations.
Tie TCK to OV
incorrect data into the device.
No connection is required for TDI, TMS, or TDO.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Figure
DD
through a 10 kΩ resistor. This prevents TCK from changing state and reading
53. If this is not possible, the isolation resistor allows future access to TRST in
System Design Information
83

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