MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 199

• Manufacturer Part Number: MC68LC060RC50
• Description: IC MPU 32BIT 68K 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Bus Operation
Figure 7-35 illustrates a flowchart for exiting the LPSTOP mode, and Figure 7-36 illustrates
the bus activity when exiting the LPSTOP mode, assuming that an interrupt is used to
awaken the processor and that the bus is initially three-stated.
Note that the acknowledge termination ignore state capability is applicable to the LPSTOP
broadcast cycle. If enabled, TA, TEA, and TRA are ignored for a user-programmed number
of BCLK cycles.
7-44
RESET
1) FETCH INITIAL SYSTEM STACK
1) FETCH PROGRAM COUNTER FROM
2) PREFETCH INSTRUCTIONS OF APPRO-
3) EXECUTE FIRST INSTRUCTION OF APPRO-
1) PERFORM INTERNAL WAKE-UP
2) BEGIN EXCEPTION PROCESSING
3) DRIVE PST4–PST0 = $18 (EXCEPTION
POINTER FROM VECTOR
TABLE
VECTOR TABLE
PRIATE EXCEPTION HANDLER
PRIATE EXCEPTION HANDLER
PROCESSING)
1) PERFORM INTERRUPT
2) PLACE STACK FRAME ON
ACKNOWLEDGE CYCLE TO
GET VECTOR NUMBER
SYSTEM STACK
PROCESSOR
Figure 7-35. Exiting LPSTOP Mode Flowchart
INTERRUPT
M68060 USER’S MANUAL
1) BEGIN TO OSCILLATE CLK FOR AT LEAST
2) TEMPORARILY CEASE ALL ALTERNATE
3) NEGATE BB, TRA, TEA, TA, CLA, BGR, BG,
4) ASSERT RSTI OR ASSERT IPL2–IPL0 TO
1) ASSERT BG AFTER PST4–PST0 = $18
2) CONTINUE ALTERNATE MASTER
1) RESPOND TO INTERRUPT ACKNOWLEDGE
2) PERFORM NORMAL READ/WRITE TO
8 CLKS PLUS 2 BCLKS
MASTER ACTIVITY
SNOOP, AVEC, MDIS, CDIS, TCI, AND TBI.
GREATER THAN INTERRUPT MASK LEVEL
ACTIVITY AS NECESSARY
BUS CYCLE AS APPROPRIATE
MEMORY AS REQUESTED BY PROCESSOR
SYSTEM
MOTOROLA