MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 233

• Manufacturer Part Number: MC68LC060RC50
• Description: IC MPU 32BIT 68K 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

SECTION 8
EXCEPTION PROCESSING
Exception processing is the activity performed by the processor in preparing to execute a
special routine for any condition that causes an exception. Exception processing does not
include execution of the routine itself. This section describes the processing for each type
of integer unit exception, exception priorities, the return from an exception, and bus fault
recovery. This section also describes the formats of the exception stack frames. For details
on floating-point exceptions refer to Section 6 Floating-Point Unit .
8.1 EXCEPTION PROCESSING OVERVIEW
Exception processing is the transition from the normal processing of a program to the pro-
cessing required for any special internal or external condition that preempts normal process-
ing. External conditions that cause exceptions are interrupts from external devices, bus
errors, and resets. Internal conditions that cause exceptions are instructions, address
errors, and tracing. For example, the TRAP, TRAPcc, CHK, RTE, DIV, and FDIV instructions
can generate exceptions as part of their normal execution. In addition, illegal instructions,
unimplemented integer instructions, unimplemented effective addresses, unimplemented
floating-point instructions and data types, and privilege violations cause exceptions. Excep-
tion processing uses an exception vector table and an exception stack frame. The following
paragraphs describe the vector table and a generalized exception stack frame.
The MC68060 uses a restart exception processing model. Exceptions are recognized at the
execution stage of the operand execution pipeline (OEP) and force later instructions that
have not yet reached that stage to be aborted.
Instructions that cannot be interrupted, such as those that generate locked bus transfers or
access noncachable precise pages, are allowed to complete before exception processing
begins, unless an access error prevents this instruction from completing.
Exception processing occurs in four functional steps. However, all individual bus cycles
associated with exception processing (vector acquisition, stacking, etc.) are not guaranteed
to occur in the order in which they are described in this section. Figure 8-1 illustrates a gen-
eral flowchart for the steps taken by the processor during exception processing.
During the first step, the processor makes an internal copy of the status register (SR). Then
the processor changes to the supervisor mode by setting the S-bit and inhibits tracing of the
exception handler by clearing the T-bit in the SR. For the reset and interrupt exceptions, the
processor also updates the interrupt priority mask in the SR.
During the second step, the processor determines the vector number for the exception. For
interrupts, the processor performs an interrupt acknowledge bus cycle to obtain the vector
MOTOROLA
M68060 USER’S MANUAL
8-1