MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 303

• Manufacturer Part Number: MC68LC060RC50
• Description: IC MPU 32BIT 68K 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

1
The MC68060 superscalar architecture allows pairs of single-cycle standard operations to
be simultaneously dispatched in the operand execution pipelines. Additionally, the design
also permits a single-cycle standard instruction plus a conditional branch (Bcc) predicted
by the branch cache to be dispatched in the OEP. Bcc instructions predicted as not taken
allow another instruction to be executed in the sOEP. This also is true for forward Bcc
instructions that are not predicted.
MOTOROLA
ANDI to SR
CINV
CPUSH
EORI to SR
MOVE from SR
MOVE to SR
MOVE USP
MOVEC
MOVES
ORI to SR
PFLUSH
PLPA
RESET
RTE
STOP
FABS, FDABS, FSABS
FADD, FDADD, FSADD
FBcc
FCMP
FDIV, FDDIV, FSDIV,
FSGLDIV
FINT, FINTRZ
FMOVE, FDMOVE, FSMOVE Move Floating-Point Data Register
FMOVE
FMOVEM
FMUL, FDMUL, FSMUL,
FSGLMUL
FNEG, FDNEG, FSNEG
FNOP
FSQRT
FSUB, FDSUB, FSSUB
FTST
These floating-point instructions are pOEP-but-allows-sOEP except for the following:
which are classified as pOEP-only
F<op>Dm,FPn
F<op>&imm,FPn
F<op>.x<mem>,FPn
Table 10-4. Superscalar Classification of M680x0 Floating-Point Instructions
Table 10-3. Superscalar Classification of M680x0 Privileged Instructions
Mnemonic
Mnemonic
AND Immediate to Status Register
Invalidate Cache Lines
Push and Invalidate Cache Lines
Exclusive OR Immediate to Status Register
Move to Status Register
Move User Stack Pointer
Move Control Register
Move Address Space
Inclusive OR Immediate to Status Register
Flush ATC Entries
Load Physical Address
Reset External Devices
Return from Exception
Load Status Register and Stop
Branch Conditionally
Compare
Divide
Move System Control Register
Move Multiple Data Registers
Multiply
No Operation
Square Root
Test Operand
Move from Status Register
Absolute Value
Add
Integer Part, Round-to-Zero
Negate
Subtract
M68060 USER’S MANUAL
Instruction
Instruction
Instruction Execution Timing
pOEP-but-allows-sOEP
pOEP-but-allows-sOEP
pOEP-but-allows-sOEP
pOEP-but-allows-sOEP
pOEP-but-allows-sOEP
pOEP-but-allows-sOEP
pOEP-but-allows-sOEP
pOEP-but-allows-sOEP
pOEP-but-allows-sOEP
pOEP-but-allows-sOEP
pOEP-but-allows-sOEP
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
pOEP-only
Superscalar Classification
Superscalar Classification
1
1
1
1
1
1
1
1
1
1
1
10-7