MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 74

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MC68LC060RC50

Manufacturer Part Number
MC68LC060RC50
Description
IC MPU 32BIT 68K 50MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68LC060RC50

Processor Type
M680x0 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
FITC—1/2-Cache Mode (Instruction ATC)
DCO—Default Cache Mode (Data Cache)
DUO—Default UPA bits (Data Cache)
DWO—Default Write Protect (Data Cache)
DCI—Default Cache Mode (Instruction Cache)
DUI—Default UPA Bits (Instruction Cache)
Bit 0—Reserved by Motorola. Always read as zero.
MOTOROLA
These bits are two user-defined bits for operand accesses (see 4.2.2.3 Descriptor Field
Definitions ).
These bits are two user-defined bits for instruction prefetch bus cycles (see 4.2.2.3
Descriptor Field Definitions )
0 = The instruction ATC operates with 64 entries.
1 = The instruction ATC operates with 32 entries.
00 = Writethrough, cachable
01 = Copyback, cachable
10 = Cache-inhibited, precise exception model
11 = Cache-inhibited, imprecise exception model
0 = Reads and writes are allowed.
1 = Reads are allowed, writes cause a protection exception.
00 = Writethrough, cachable
01 = Copyback, cachable
10 = Cache-inhibited, precise exception model
11 = Cache-inhibited, imprecise exception model
M68060 USER’S MANUAL
Memory Management Unit
4-5

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