MC68LC060RC50 Freescale Semiconductor, MC68LC060RC50 Datasheet - Page 336

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MC68LC060RC50

Manufacturer Part Number
MC68LC060RC50
Description
IC MPU 32BIT 68K 50MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68LC060RC50

Processor Type
M680x0 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Applications Information
11.2.6 Clocking
For systems which have PCLK-to-BCLK skew controlled by a phase-locked-loop (PLL)
clock generator such as the 88915 or 88916, it is possible to connect the PCLK of the
MC68040 to the MC68060 CLK input as shown in Figure 11-8. Otherwise, the MC68060
CLK must be generated by an 88915 PLL as shown in Figure 11-9.
Appropriate generation of the CLKEN signal to enable 1/2-speed operation is easily
achieved by delaying the MC68040 BCLK by 5 ns before feeding it into the CLKEN input of
the MC68060.
Be aware that a clock skew exists between CLK and BCLK. The MC88915 can only control
the skew to within 1 ns. Figure 11-10 shows the relationship between BCLK and CLKEN.
11.2.7 PSTx Encoding
PSTx signal encoding is different between the MC68060 and MC68040. This should not
affect normal applications because PSTx signals are not used for bus control logic.
11-14
EXISTING
MC68040
SYSTEM
BCLK
EXISTING
MC68040
SYSTEM
Figure 11-9. Generic CLK Generation
Figure 11-8. Simple CLK Generation
BCLK
PCLK
VIRTUAL MC68040
M68060 USER’S MANUAL
FEEDBACK
SYNC0
VIRTUAL MC68040
2XQ
Q0
5 NS
CLKEN
CLK
5 ns
MC68060
CLKEN
CLK
MC68060
MOTOROLA

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