MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 104

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Bus Operation
State 3—The QUICC asserts DS during S3, indicating that data is stable on the data bus.
As long as at least one of the DSACKx signals is recognized by the end of S2 (meeting the
asynchronous input setup time requirement), the cycle terminates one clock later. If
DSACKx is not recognized by the start of S3, the QUICC inserts wait states instead of pro-
ceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACK0
must remain negated throughout the asynchronous input setup and hold times around the
end of S2. If wait states are added, the QUICC continues to sample DSACKx on the falling
edges of the clock until one is recognized. The selected device uses the four write enables
lines or R/W, SIZ1, SIZ0, A1, and A0 to latch data from the appropriate byte(s) of the data
bus (D31–D24, D23–D16, D15–D8, and D7–D0). WE3–WE0 or SIZ1, SIZ0, A1, and A0
select the bytes of the data bus. If it has not already done so, the device asserts DSACKx
to signal that it has successfully stored the data.
State 4—The QUICC issues no new control signals during S4.
State 5—The QUICC negates WE3–WE0, AS, and DS during S5. It holds the address and
data valid during S5 to provide address hold time for memory systems. R/W, SIZ1, SIZ0,
and FC3–FC0 also remain valid throughout S5. The external device must keep DSACKx
asserted until it detects the negation of AS or DS (whichever it detects first). The device must
negate DSACKx within approximately one clock period after sensing the negation of AS or
DS. DSACKx signals that remain asserted beyond this limit may be prematurely detected
for the next bus cycle.
4.3.3 Read-Modify-Write Cycle
The read-modify-write cycle performs a read, conditionally modifies the data in the arith-
metic logic unit, and may write the data out to memory. In the QUICC, this operation is indi-
visible, providing semaphore capabilities for multiprocessor systems. During the entire read-
modify-write sequence, the QUICC asserts RMC to indicate that an indivisible operation is
occurring. The QUICC does not issue a bus grant (BG) signal in response to a bus request
(BR) signal during this operation. Figure 4-21 is an example of a functional timing diagram
of a read-modify-write instruction specified in terms of clock periods.
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MC68360 USER’S MANUAL
MOTOROLA
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