MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 312

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

System Integration Module (SIM60)
Table 6-12 summarizes the effects of the various combinations of the SYNC bit in the GMR
and the BSTM bit in the MCR.)
OPAR—Odd Parity
PBEE—Parity Bus Error Enable
TSS40—TS Sample (MC68EC040)
6-68
When the SRAM controller is used, CS and DSACK assertion and negation timings are
synchronous. The CSNTQ and the TRLXQ attributes may be set as desired.
When the DRAM controller is used, CAS and DSACK are negated synchronously to the
QUICC clock.
Only when the SYNC bit is set, is parity support possible for an external MC68030-type
master.
This attribute is used to program odd or even parity. It may also be used to generate parity
errors for testing purposes by writing the DRAM/SRAM with OPAR = 1 and reading the
DRAM/SRAM with OPAR = 0.
This attribute is used to enable an internal bus error if a parity error is detected. It is ap-
plicable only when the QUICC is the bus master; if in slave mode the PERR will be as-
serted if the parity function is enabled but it will not cause bus error regardless of the
setting of this bit. The BERR signal will be internally asserted on the memory read cycle.
This attribute is used to control the MC68EC040 cycles. When the MC68EC040 address
to clock setup timing does not meet the memory controller decoding time, the memory
NOTES:
If Synchronous bus mode is selected, glue logic is required for external MC68030-type bus master (including
MC68360) ensuring that proper set up time for address strobe assertion is met
1 = Synchronous operation of the memory controller (external MC68030-type
0 = Even parity
1 = Odd parity
0 = Disable internal bus error.
1 = Enable internal bus error.
SYNC-BSTM
master only).
00
01
10
11
Using the internal bus error requires a longer data setup time for
read cycles.
External MC68030-type master is running synchronously with the QUICC, and the user desires
to make external-to-external SRAM accesses as fast as possible. The CSNTQ and TRLXQ at-
tributes may not be used. Does not affect DRAM performance. Parity support is not available.
Not as fast as case 01, but CSNTQ and TRLXQ attributes may be used. Parity support is avail-
able.
MC68030-type master and QUICC can be asynchronous. Lowest performance, since the ex-
ternal AS signal is synchronized prior to being used. Parity support is not available.
Do not use.
Table 6-12. SYNC-BSTM Bit Combination Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
(MC68030-Type External Master)
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Result
MOTOROLA