MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 270

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

System Integration Module (SIM60)
6.8.4 Interrupts in Slave Mode
The SIM60 interrupt controller continues to function in slave mode and can present inter-
rupts from the PIT, SWT, and external interrupt sources on the IRQx pins to the processor.
The highest priority request is output as an encoded value on the IOUTx pins or is output on
a single RQOUT pin.
The CPM will also generate interrupts in slave mode. The CPM always generates unique
vectors for its sub-modules in slave mode. The CPM also offers a number of individual inter-
rupt request inputs (port C pins) that may be used in slave mode.
When the SIM60 is in slave mode, the PIT and SWT must also generate interrupt vectors.
For the IRQx pins, no vector is output in slave mode; rather, the AVECO pin is asserted if
the corresponding bit in the AVR is set.
One important restriction must be adhered to in slave mode. The user should not utilize an
IRQx pin that is on the same level as the CPM, PIT, or SWT. The level of the CPM is pro-
grammed in the CICR. The level of the PIT is programmed in the PICR. The level of the SWT
is 7 if it generates interrupts. Note that CPM port C pins operate similarly to the IRQx pins
and may still be used.
6.8.5 Pin Differences in Slave Mode
A number of signals change functionality in slave mode. See Section 2 Signal Descriptions
for a full listing. A partial list of functionality changes is as follows:
6-26
1. BR will be an output from the QUICC (refresh cycles, IDMA, and SDMA) to the external
2. BG will be an input to the QUICC (refresh cycles, IDMA, and SDMA) from the external
3. BGACK will be asserted during the QUICC external bus cycles.
4. The QUICC interrupt controller will output its interrupt requests on the IOUT2–IOUT0
5. An AVEC output (AVECO) function is supported instead of the AVEC input pin.
6. The breakpoint logic may monitor the external bus instead of the internal bus and as-
7. The three-state (TRIS) pin becomes the transfer start (TS) pin in slave mode. Anytime
bus.
bus.
pins, which normally would be sent to the CPU32+ core, and will reflect internally the
interrupt acknowledge cycle. The three IOUTx pins reflect the seven interrupt request
levels. The IOUTx pins can be output on the IRQ1, IRQ4, and IRQ6 pins or on the par-
ity PRTY2–PRTY0 pins as programmed in the port E pin assignment register. Addi-
tionally, the QUICC interrupt controller can output its interrupt requests on one
interrupt request pin (RQOUT) instead of three pins.
sert the BKPTO pin.
BR is still an input in MC68040 companion mode.
BG is still an output in MC68040 companion mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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