MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 422

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Serial Interface with Time Slot Assigner
are enabled by the SI RAM and will not drive L1TXDx; otherwise, L1TXDx is an open-drain
output and should be pulled high externally.
The QUICC supports contention detection on the D channel of the SCIT bus. When the
QUICC has data to transmit on the D channel, it checks a SCIT bus bit that is marked with
a special route code (generally, bit 4 of C/I channel 2). The physical layer device monitors
the physical layer bus for activity on the D channel and indicates on this bit that the channel
is free. If a collision is detected on the D channel, the physical layer device sets bit 4 of C/I
channel 2 to logic high The QUICC then aborts its transmission and retransmits the frame
when this bit is set again. This procedure is handled automatically for the first two buffers of
a frame.
7.8.7.1 SI GCI ACTIVATION/DEACTIVATION PROCEDURE. In the deactivated state, the
clock pulse is disabled and the data line is at a logic one. The layer 1 device activates the
QUICC by enabling the clock pulses and by an indication in the channel 0 C/I channel. The
QUICC will report to the CPU32+ core by a maskable interrupt that a valid indication is in
the SMC receive BD.
When the CPU32+ core activates the line, the data output of L1TXDn is programmed to zero
by setting the STZx bit in the SIMODE register. Code 0 (command timing TIM) will be trans-
mitted on channel 0 C/I channel to the layer 1 device until the STZx bit is reset. The physical
layer device will resume the clock pulses and will give an indication in the channel 0 C/I
channel. The CPU32+ core should reset the STZx bit to enable data output.
7.8.7.2 SI GCI PROGRAMMING. The following paragraphs describe programming for both
the normal mode GCI and SCIT.
7.8.7.2.1 Normal Mode GCI Programming. The user can program the channels used for
the GCI bus interface to the appropriate configuration. First, the user should program the
SIMODE to the GCI/SCIT mode for that channel, using the DSCx, FEx, CEx, and RFSDx
bits. This mode defines the sync pulse to GCI sync for framing and data clock as one-half
the input clock rate. The user can program more than one channel to interface to the GCI
bus. Also, if the receive and transmit section are used for interfacing the same GCI bus, the
user can internally connect the receive clock and sync signals to the SI RAM transmit sec-
tion, using the CRTx bits. The user should then define the GCI frame routing and strobe
select using the SI RAM. When the receive and transmit section use the same clock and
sync signals, the user should program the receive section as well as the transmit section to
the same configuration. The L1TXDx pin in the I/O register should be programmed to be an
open-drain output. To support the monitor and the C/I channels in GCI, the user should route
those channels to one of the SMCs. To support the D channel when there is no possibility
of collision, the user should clear the GRx bit corresponding to the SCC that supports the D
channel in the SIMODE.
7.8.7.2.2 SCIT Programming. For interfacing the GCI/SCIT bus, the user should program
the SIMODE to the GCI/SCIT mode. The SI RAM is programmed to support a 96-bit frame
length, and the frame sync is programmed to the GCI sync pulse. Generally, the SCIT bus
supports the D channel access collision mechanism. For this purpose, the user should pro-
gram the receive and transmit sections to use the same clock and sync signals, using the
7-98
MC68360 USER’S MANUAL
MOTOROLA
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