MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 261

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

The general system clock can switch automatically from low to high frequency whenever
one of the following conditions exists:
When neither of these conditions exists, the general system clock automatically switches
back to the low frequency.
When the general system clock is divided, its duty cycle is changed. One phase remains the
same (e.g., 20 ns @ 25 MHz); the other becomes longer. Note that the CLKO1 and CLKO2
pins no longer have a 50% duty cycle when the general system clock is divided (see Figure
6-8).
6.5.5.3 BRGCLK. The BRGCLK is used by the five CPM baud rate generators. There are
four SCC/SCM baud rate generators and one SPI baud rate generator. BRGCLK defaults
to VCO/2 = 25 MHz (assuming a 25-MHz system frequency). The purpose of BRGCLK is to
allow the five baud rate generators to continue to operate at a fixed frequency, even when
the rest of the QUICC is operating at a reduced frequency (i.e., the general system clock is
divided). See 7.9 Baud Rate Generators (BRGs) for more information on how to save power
using the BRGCLK.
6.5.5.4 SYNCCLK. The SyncCLK is used by the serial synchronization circuitry in the serial
ports of the CPM, including the SI, SCCs, and SMCs. The SyncCLK performs the function
of synchronizing externally generated clocks before they are used internally. SyncCLK
defaults to VCO/2 = 25 MHz (assuming a 25-MHz system frequency).
The purpose of SyncCLK is to allow the SI, SCCs, and SMCs to continue to operate at a
fixed frequency, even when the rest of the QUICC is operating at a reduced frequency.
Thus, SyncCLK allows the user to maintain the serial synchronization circuitry at the desired
rate, while lowering the general system clock to the lowest possible rate. However, the Sync-
CLK frequency must always be at least as high as the general system clock frequency.
MOTOROLA
• The level of the pending or current interrupt is higher than the INTEN bits in CDVCR.
• The CPM RISC controller has a pending request or is currently executing a routine (i.e.,
it is not idle). This option is maskable by the RRQEN bit in CDVCR.
During early board prototyping, the user should leave BRGCLK
at its standard frequency (e.g., 25 MHz) for the sake of simplici-
ty.
Within the four SCC/SMC baud rate generators, the user should
not use a baud rate generator divider equal to 1, unless the
BRGCLK is at the maximum frequency.
DIVIDE BY 1
DIVIDE BY 2
DIVIDE BY 4
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 6-8. Divided Clocks
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
System Integration Module (SIM60)
6-17