MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 690

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Parallel I/O Ports
All PCDIR bits and PCPAR bits are cleared on total system reset, configuring all port pins
as general-purpose input pins. Note that the global CIMR is also cleared on total system
reset so that, if any PCIO pin is left floating, it will not cause a false interrupt.
If a port C pin is selected as a general-purpose I/O pin, it may be accessed through the port
C data register (PCDAT). Data written to the PCDAT is stored in an output latch. If a port C
pin is configured as an output, the output latch data is gated onto the port pin. In this case,
when PCDAT is read,the port pin itself is read. If a port C pin is configured as an input, data
written to PCDAT is still stored in the output latch but is prevented from reaching the port
pin. In this case, when PCDAT is read, the state of the port pin is read.
To configure a port C pin an a general-purpose output pin, use the following steps. Note that
when the pin is configured as an output, port C interrupts are not possible.
To configure a port C pin as a general-purpose input pin that does not generate an interrupt,
use the following steps:
When a port C pin is configured as a general-purpose I/O input, a change according to the
port C interrupt register (PCINT) will cause an interrupt request signal to be sent to the CPM
interrupt controller. Each port C line can be programmed to assert an interrupt request upon
a high-to-low change or any change. Each port C line asserts a unique interrupt request to
the CPM interrupt pending register and has a different internal interrupt priority level within
the CPM interrupt controller. See 7.15 CPM Interrupt Controller (CPIC) for more details.
Each request can be masked independently in the CPM interrupt mask register.
To configure a port C pin an a general-purpose input pin that generates an interrupt, use the
following steps:
7-366
1. Write the corresponding PCPAR bit with a zero.
2. Write the corresponding PCDIR bit with a one.
3. Write the corresponding PCSO bit with a zero (for the sake of clarity).
4. The corresponding PCINT bit is a don’t care.
5. Write the pin value using the PCDAT.
1. Write the corresponding PCPAR bit with a zero.
2. Write the corresponding PCDIR bit with a zero.
3. Write the corresponding PCSO bit with a zero.
4. The corresponding PCINT bit is a don’t care.
5. Write the corresponding CIMR bit with a zero to prevent interrupts from being gener-
6. Read the pin value using the PCDAT.
1. Write the corresponding PCPAR bit with a zero.
2. Write the corresponding PCDIR bit with a zero.
3. Write the corresponding PCSO bit with a zero.
ated to the CPU32+ core.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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