MC68MH360EM33L Freescale Semiconductor, MC68MH360EM33L Datasheet - Page 338

• Manufacturer Part Number: MC68MH360EM33L
• Description: IC MPU QUICC ETHER 33MHZ 240FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360EM33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

RISC Timer Tables
Bits 29–20—Reserved
Bits 19–16—Timer Number
Bits 15–0—Timer Period
TM_cnt. This value is simply a tick counter that is updated by the RISC after each tick. It is
updated if the RISC internal timer is enabled, regardless of whether any of the 16 timers are
enabled. It can be used to track the number of ticks that the RISC has received and
responded to. This value is updated only after the RISC scans the timer table.
7.4.2 RISC Timer Table Entries
The actual 16 timers themselves are located in the block of memory following the TM_BASE
location. Each timer occupies 4 bytes. The first word forms the initial value of the timer writ-
ten during the execution of the SET TIMER command, and the next word is the current value
of the timer, which is decremented until it reaches zero. These locations should not be mod-
ified by the user; they are documented only as a debugging aid for user code.
7.4.3 RISC Timer Event Register (RTER)
This 16-bit register is used to report events recognized by the 16 timers and to generate
interrupts. Bit 0 corresponds to timer 0, and bit 15 corresponds to timer 15. Note that an
interrupt will only be generated if the RISC timer table bit is set in the CPM interrupt mask
register. RTER may be read at any time. A bit is cleared by writing a one (writing a zero does
not affect a bit’s value), and more than one bit may be cleared at a time. This register is
cleared at reset.
7.4.4 RISC Timer Mask Register (RTMR)
This 16-bit register is used to enable interrupts that may be generated in the RISC timer
event register. If a bit is set, it enables the corresponding interrupt in the RTER. If a bit is
cleared, it masks the corresponding interrupt in the RTER. Note that an interrupt will only be
generated if the RISC timer table bit is set in the CPM interrupt mask register. This read-
write register is cleared at reset.
7.4.5 SET TIMER Command
This command is used to enable, disable, and configure the 16 timers in the RISC timer ta-
ble. The SET TIMER command is issued to the CR. This means the value $
written to CR. However, before writing this value, the TM_cmd value should be set up by the user. See 7.4.1
RISC Timer Table Parameter RAM for details.
7.4.6 RISC Timer Initialization Sequence
The following sequence initializes the RISC timers:
7-14
These bits should be written with zeros.
The timer number is a value from 0 to 15 that signifies the timer is configured.
The timer period is the 16-bit timeout value of the timer. The maximum value is 65536,
which is programmed by writing $0000 to the timer period.
1. Configure the RCCR to determine the desired tick interval that will be used for the en-
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0851 should be
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