CS4271-CZZ Cirrus Logic Inc, CS4271-CZZ Datasheet - Page 28

• Manufacturer Part Number: CS4271-CZZ
• Description: IC CODEC AUD 24BIT 114DB 28TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4271-CZZ

• Package / Case: 28-TSSOP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 108 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 98 dB ADC / - 100 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1003 - EVAL BOARD CS4271 STEREO CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1041-5

To operate the CS4271 with an externally generated MCLK signal, no crystal should be used, XTI should be con-
nected to ground and XTO should be left unconnected. In this configuration, MCLK is an input and must be driven
externally with an appropriate speed clock.
5.2.3.2
Depending on the use of an external crystal, or whether the CS4271 is in Master or Slave Mode, different
MCKL/LRCK and SCLK/LRCK ratios may be used. These ratios as well as the Control Port Register Bits that must
be set in order to obtain them are shown in Tables 8 and 9 below.
Notes: 25. For the Ratio1 and Ratio0 bits listed above, “d” indicates that any value may written.
28
Double Speed
Double Speed
Single Speed
Single Speed
Quad Speed
Quad Speed
Clock Ratio Selection
Table 8. Clock Ratios - Control Port Mode With External Crystal
MCLK/LRCK
MCLK/LRCK
256
512
128
256
128
256
512
128
256
128
Double Speed
External Crystal Used, MCLK=Output
Single Speed
Quad Speed
Mode
Table 7. Crystal Frequencies
SCLK/LRCK
SCLK/LRCK
32, 64, 128
32, 64, 128
32, 64
32, 64
32, 64
Master Mode
Slave Mode
64
64
64
64
64
Crystal Frequency
512 x Fs
256 x Fs
128 x Fs
LRCK
LRCK
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Fs
Ratio1 Bit
Ratio1 Bit
d
d
0
1
0
1
0
1
0
1
25
25
Ratio0 Bit
Ratio0 Bit
CS4271
d
d
d
d
d
d
d
d
d
d
DS592F1
25
25
25
25
25
25
25
25
25
25