CS4271-CZZ Cirrus Logic Inc, CS4271-CZZ Datasheet - Page 36

• Manufacturer Part Number: CS4271-CZZ
• Description: IC CODEC AUD 24BIT 114DB 28TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4271-CZZ

• Package / Case: 28-TSSOP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 108 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 98 dB ADC / - 100 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1003 - EVAL BOARD CS4271 STEREO CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1041-5

6.2
In I²C mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock
to data relationship as shown in Figure 18. There is no CS pin. Pin AD0 forms the partial chip address and should be
tied to VA or AGND as required. The upper 6 bits of the 7-bit address field must be 001000. To communicate with the
CS4271, the LSB of the chip address field, which is the first byte sent to the CS4271, should match the setting of the
AD0 pin. The eighth bit of the address byte is the R/W bit (high for a read, low for a write). If the operation is a write,
the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then
followed by the data to be written. If the operation is a read, then the contents of the register pointed to by the MAP will
be output after the chip address.
The CS4271 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP
will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte is written, al-
lowing block reads or writes of successive registers.
36
INCR - Auto MAP Increment Enable
MAP(3:0) - Memory Address Pointer
INCR
7
0
I²C
Default = ‘0’.
0 - Disabled
1 - Enabled
Default = ‘0000’.
Mode
Reserved
SDA
SCL
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
6
0
Start
001000
Reserved
Table 10. Memory Address Pointer (MAP)
5
0
Figure 18. Control Port Timing,
ADDR
AD0
Reserved
R/W
4
0
ACK
DATA
1-8
MAP3
3
0
Note 1
ACK
I²C
Mode
DATA
1-8
MAP2
2
0
ACK
Stop
MAP1
1
0
CS4271
MAP0
DS592F1
0
0