CS4271-CZZ Cirrus Logic Inc, CS4271-CZZ Datasheet - Page 35

• Manufacturer Part Number: CS4271-CZZ
• Description: IC CODEC AUD 24BIT 114DB 28TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4271-CZZ

• Package / Case: 28-TSSOP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 108 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 98 dB ADC / - 100 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1003 - EVAL BOARD CS4271 STEREO CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1041-5

6. CONTROL PORT INTERFACE
The Control Port is used to load all the internal settings of the CS4271. The operation of the Control Port may be
completely asynchronous to the audio sample rate. However, to avoid potential interference problems, the Control
Port pins should remain static if no operation is required.
The Control Port has 2 modes: SPI and I²C, with the CS4271 operating as a slave to control messages in both
modes. If I²C operation is desired, AD0/CS should be tied to VA or AGND. If the CS4271 ever detects a high to low
transition on AD0/CS after power-up, SPI mode will be selected. The Control Port registers are write-only in SPI
mode.
Upon release of the RST pin, the CS4271 will wait approximately 10 ms before it begins its start-up sequence. The
part defaults to Stand-Alone Mode, in which all operational modes are controlled as described under “Stand-Alone
Mode” on page 24. The Control Port is active at all times, and if bit 1 of register 07h (CPEN) is set, the part enters
Control-Port Mode and all operational modes are controlled by the Control Port registers. This bit can be set at any
time, but to avoid unpredictable output noises, bit 1 (CPEN) and bit 0 (PDN) of register 07h should be set by writing
03h before the end of the 10 ms start-up wait period. All registers can then be set as desired before releasing the
PDN bit to begin the start-up sequence. If system requirements do not allow writing to the control port immediately
following the release of RST, the SDIN line should be held at logic “0” until the proper serial mode can be selected.
6.1
In SPI mode, CS is the CS4271 chip select signal, CCLK is the control port bit clock, CDIN is the input data line from
the microcontroller and the chip address is 0010000. All control signals are inputs and data is clocked in on the rising
edge of CCLK.
Figure 17 shows the operation of the Control Port in SPI mode. To write to a register, bring CS low. The first 7 bits
on CDIN form the chip address, and must be 0010000. The eighth bit is a read/write indicator (R/W), which must be
low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that
is to be updated. The next 8 bits are the data which will be placed into the register designated by the MAP. See
Table 10 on page 36.
The CS4271 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP
will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte is written, al-
lowing block writes to successive registers.
DS592F1
SPI Mode
CCLK
CS
CDIN
Figure 17. Control Port Timing, SPI mode
MAP = Memory Address Pointer
ADDRESS
0010000
CHIP
R/W
MAP
MSB
byte 1
DATA
byte n
LSB
CS4271
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