CS4271-CZZ Cirrus Logic Inc, CS4271-CZZ Datasheet - Page 4

• Manufacturer Part Number: CS4271-CZZ
• Description: IC CODEC AUD 24BIT 114DB 28TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4271-CZZ

• Package / Case: 28-TSSOP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 108 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 98 dB ADC / - 100 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1003 - EVAL BOARD CS4271 STEREO CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1041-5

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7. REGISTER QUICK REFERENCE .......................................................................................... 37
8. REGISTER DESCRIPTION .................................................................................................... 38
9. PARAMETER DEFINITIONS .................................................................................................. 45
10. PACKAGE DIMENSIONS ..................................................................................................... 46
11. APPENDIX ............................................................................................................................ 47
6.1 SPI Mode ......................................................................................................................... 35
6.2 I²C Mode .......................................................................................................................... 36
8.1 Mode Control 1 - Address 01h ......................................................................................... 38
8.2 DAC Control - Address 02h ............................................................................................. 39
8.3 DAC Volume & Mixing Control - Address 03h ................................................................. 40
8.4 DAC Channel A Volume Control - Address 04h .............................................................. 42
8.5 DAC Channel B Volume Control - Address 05h .............................................................. 42
8.6 ADC Control - Address 06h ............................................................................................. 43
8.7 Mode Control 2 - Address 07h ......................................................................................... 43
8.8 Chip ID - Register 08h ..................................................................................................... 44
8.1.1 Functional Mode (Bits 7:6) .................................................................................. 38
8.1.2 Ratio Select (Bits 5:4) ......................................................................................... 38
8.1.3 Master / Slave Mode (Bit 3) ................................................................................. 38
8.1.4 DAC Digital Interface Format (Bits 2:0) ............................................................... 38
8.2.1 Auto-Mute (Bit 7) ................................................................................................. 39
8.2.2 Interpolation Filter Select (Bit 6) .......................................................................... 39
8.2.3 De-Emphasis Control (Bits 5:4) ........................................................................... 39
8.2.4 Soft Volume Ramp-Up After Error (Bit 3) ............................................................ 40
8.2.5 Soft Ramp-Down Before Filter Mode Change (Bit 2) .......................................... 40
8.2.6 Invert Signal Polarity (Bits 1:0) ............................................................................ 40
8.3.1 Channel B Volume = Channel A Volume (Bit 6) ................................................. 40
8.3.2 Soft Ramp or Zero Cross Enable (Bits 5:4) ......................................................... 40
8.3.3 ATAPI Channel Mixing and Muting (Bits 3:0) ...................................................... 41
8.5.1 Mute (Bit 7) .......................................................................................................... 42
8.5.2 Volume Control (Bits 6:0) .................................................................................... 42
8.6.1 Dither for 16-Bit Data (Bit 5) ................................................................................ 43
8.6.2 ADC Digital Interface Format (Bit 4) .................................................................... 43
8.6.3 ADC Channel A & B Mute (Bits 3:2) .................................................................... 43
8.6.4 Channel A & B High Pass Filter Disable (Bits 1:0) .............................................. 43
8.7.1 Digital Loopback (Bit 4) ....................................................................................... 43
8.7.2 AMUTEC = BMUTEC (Bit 3) ............................................................................... 43
8.7.3 Freeze (Bit 2) ...................................................................................................... 44
8.7.4 Control Port Enable (Bit 1) .................................................................................. 44
8.7.5 Power Down (Bit 0) ............................................................................................. 44
8.8.1 Chip ID (Bits 7:4) ................................................................................................. 44
8.8.2 Chip Revision (Bits 3:0) ....................................................................................... 44
CS4271
DS592F1