UDA1355H/N2,557 NXP Semiconductors, UDA1355H/N2,557 Datasheet - Page 12

• Manufacturer Part Number: UDA1355H/N2,557
• Description: IC CODEC STER/SUDIO SPDIF 44QFP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1355H/N2,557

• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 98
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935271552557

NXP Semiconductors
7.3.2
The PLL locks on the incoming digital data of the SPDIF or
WS input signal. The PLL recovers the clock from the
SPDIF or WSI signal and removes jitter to produce a stable
system clock (see Fig.4).
7.3.3
This circuit is clocked by the 12.288 MHz crystal oscillator
clock and generates a Word Selection (WS) detection
signal. If the WS detector does not detect any WS edge,
defined as 7 times LOW and 7 times HIGH, then the
WS detection signal is LOW. This information can be used
to set the clock for the noise shaper in the interpolator. This
will prevent noise shaper noise in the audio band.
2003 Apr 10
handbook, halfpage
SPDIF0
SPDIF1
SPDIF2
SPDIF3
Stereo audio codec with SPDIF interface
XTALOUT
WSI
XTALIN
CLK_OUT
12.288 MHz
PLL
W
Fig.3 Crystal oscillator clock system.
23
24
25
26
2
ORD SELECTION DETECTION CIRCUIT
select SPDIF source
CLOCK SYSTEM
SLICER
Fig.4 PLL clock system.
13
14
11
L3-bus or I
register setting
OSCILLATOR
CRYSTAL
2
C-bus
256f s or 384f s clock
PLL clock
DECODER
IEC 60958
PLL
UDA1355H
MODULE
UDA1355H
PLL
MGU830
256f s
384f s
MGU827
or
12
7.3.4
The UDA1355H has a clock output pin (pin CLK_OUT),
which can be used to drive other audio devices in the
system. In microcontroller mode the output clock is
256f
32, 44.1 and 48 kHz.
The source of the output clock is either the crystal
oscillator or the PLL, depending on the selected
application and control mode.
7.4
The UDA1355H IEC 60958 decoder can select one of four
SPDIF input channels. An on-chip amplifier with hysteresis
amplifies the SPDIF input signal to CMOS level, making it
possible to accept both analog and digital SPDIF signals
(see Fig.5).
7.4.1
From the incoming SPDIF bitstream 24 bits of data for the
left and right channel are extracted.
There is a hard mute (not a cosine roll-off mute) if the
IEC 60958 decoder is out of lock or detects bi-mark phase
encoding violations. The lock indicator and the key
channel status bits are accessible in L3-bus mode.
The UDA1355H supports the following sample
frequencies and data rates, including half and double of
these frequencies:
• f
• f
• f
handbook, halfpage
s
s
s
75 Ω
s
= 32 kHz; resulting in a data rate of 2.048 Mbit/s
= 44.1 kHz; resulting in a data rate of 2.8224 Mbit/s
= 48 kHz; resulting in a data rate of 3.072 Mbit/s.
or 384f
IEC 60958 decoder
C
A
UDIO DATA
LOCK OUTPUT
s
. In static mode the output clock is 256 times
Fig.5 IEC 60958 input circuit.
180 pF
10 nF
SPDIF0
SPDIF1
SPDIF2
SPDIF3
23
24
25
26
Preliminary specification
UDA1355H
UDA1355H
MGU829