UDA1355H/N2,557 NXP Semiconductors, UDA1355H/N2,557 Datasheet - Page 53

• Manufacturer Part Number: UDA1355H/N2,557
• Description: IC CODEC STER/SUDIO SPDIF 44QFP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1355H/N2,557

• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 98
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935271552557

NXP Semiconductors
Table 58 Description of register bits (address 20H)
Table 59 ADC volume control settings
Table 60 Register address 21H
2003 Apr 10
Symbol
Default
Symbol
Default
15 to 8 MA_DECL[7:0]
7 to 0
Stereo audio codec with SPDIF interface
DECR7
DECL7
BIT
BIT
BIT
MA_
MA_
0
0
0
0
0
0
1
1
1
1
1
1
:
:
MA_DECR[7:0]
MT_ADC
SYMBOL
15
0
7
−
0
DECR6
DECL6
MA_
MA_
0
0
0
0
0
0
1
0
0
0
0
0
:
:
14
−
0
6
−
0
ADC volume setting left channel. Value to program the ADC gain setting for the left
channel. The range is from +24 to −63 dB and −∞ dB (see Table 59).
ADC volume setting right channel. Value to program the ADC gain setting for the right
channel. The range is from +24 to −63 dB and −∞ dB (see Table 59).
DECR5
DECL5
MA_
MA_
1
1
1
0
0
0
1
0
0
0
0
0
:
:
13
−
0
5
−
0
DECR4
DECL4
MA_
MA_
1
0
0
0
0
0
1
0
0
0
0
0
:
:
12
−
0
4
−
0
DECR3
DECL3
MA_
MA_
53
0
1
1
0
0
0
1
0
0
0
0
0
:
:
PGA_GAIN_
PGA_GAIN_
CTRLR3
CTRLL3
11
0
3
0
DESCRIPTION
DECR2
DECL2
MA_
MA_
0
1
1
0
0
0
1
1
0
0
0
0
:
:
PGA_GAIN_
PGA_GAIN_
CTRLR2
CTRLL2
10
0
2
0
DECR1
DECL1
MA_
MA_
0
1
1
1
0
0
1
0
1
1
0
0
:
:
PGA_GAIN_
PGA_GAIN_
CTRLR1
CTRLL1
Preliminary specification
9
0
1
0
DECR0
DECL0
MA_
MA_
0
1
0
0
1
0
1
0
1
0
1
0
UDA1355H
:
:
PGA_GAIN_
PGA_GAIN_
CTRLR0
CTRLL0
GAIN (dB)
+24.0
+23.5
+23.0
:
+1.0
+0.5
0
−0.5
:
−62.0
−62.5
−63.0
−63.5
−∞
8
0
0
0