UDA1355H/N2,557 NXP Semiconductors, UDA1355H/N2,557 Datasheet - Page 3

• Manufacturer Part Number: UDA1355H/N2,557
• Description: IC CODEC STER/SUDIO SPDIF 44QFP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1355H/N2,557

• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 98
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935271552557

NXP Semiconductors
1
1.1
• 2.7 to 3.6 V power supply
• Integrated digital interpolator filter and Digital-to-Analog
• 24-bit data path in interpolator
• No analog post filtering required for DAC
• Integrated Analog-to-Digital Converter (ADC),
• 24-bit data path in decimator
• Master or slave mode for digital audio data I/O interface
• I
1.2
• Controlled by means of static pins or microcontroller
1.3
• On-chip amplifier for converting IEC 60958 input to
• Supports level I, II and III timing
• Selectable IEC 60958 input channel, one of four
• Supports input frequencies from 28 to 96 kHz
• Lock indication signal available on pin LOCK
• 40 status bits can be read for left and right channel via
• Channel status bits available via L3-bus or I
• Pre-emphasis information of incoming IEC 60958
• Detection of digital data preamble, such as AC3,
1.4
• CMOS output level converted to IEC 60958 output
• Full-swing digital signal, with level II timing using crystal
• 32, 44.1 and 48 kHz output frequencies supported in
2003 Apr 10
Converter (DAC)
Programmable Gain Amplifier (PGA) and digital
decimator filter
and 24 bits formats supported on digital I/O interface.
(L3-bus or I
CMOS levels
L3-bus or I
pre-emphasis, audio sample frequency, two channel
Pulse Code Modulation (PCM) indication and clock
accuracy
bitstream available in register
available on pin in microcontroller mode.
signal
oscillator clock
static mode
Stereo audio codec with SPDIF interface
2
S-bus, MSB-justified, LSB-justified 16, 18, 20,
FEATURES
General
Control
IEC 60958 input
IEC 60958 output
2
2
C-bus
C-bus) interface.
2
C-bus: lock,
3
• 32, 44.1 and 48 kHz output frequencies (including
• Via microcontroller, 40 status bits can be set for left and
1.5
• Supports sampling frequencies from 16 to 100 kHz
• Supported static mode:
• Supported microcontroller mode:
• BCK and WS signals can be slave or master, depending
1.6
• Supports sampling frequencies from 16 to 100 kHz
• Analog front-end includes a 0 to +24 dB PGA in steps of
• Digital independent left and right volume control of
• Bitstream ADC operating at 64f
• Comb filter decreases sample rate from 64f
• Decimator filter (8f
1.7
• Digital de-emphasis for 32, 44.1, 48 and 96 kHz audio
• Automatic de-emphasis when using IEC 60958 to DAC
• Soft mute made of a cosine roll-off circuit selectable via
double and half of these frequencies) supported in
microcontroller mode
right channel.
– I
– LSB-justified 16 and 24 bits format
– MSB-justified format.
– I
– LSB-justified 16, 18, 20 or 24 bits format
– MSB-justified format.
on application mode.
3 dB, selectable via microcontroller interface
+24 to −63.5 dB in steps of 0.5 dB via microcontroller
interface
half-band filters.
sampling frequencies
pin MUTE or L3-bus interface
2
2
S-bus format
S-bus format
Digital I/O interface
DAC digital sound processing
ADC digital sound processing
s
to f
s
) made of a cascade of three FIR
Preliminary specification
s
UDA1355H
s
to 8f
s