UDA1355H/N2,557 NXP Semiconductors, UDA1355H/N2,557 Datasheet - Page 44

• Manufacturer Part Number: UDA1355H/N2,557
• Description: IC CODEC STER/SUDIO SPDIF 44QFP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1355H/N2,557

• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 98
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935271552557

NXP Semiconductors
Table 33 Register address 04H
Table 34 Description of register bits (address 04H)
2003 Apr 10
Symbol
Default
Symbol
Default
14 to 11 −
2 to 0
5 to 3
Stereo audio codec with SPDIF interface
BIT
BIT
BIT
BIT
15
10
9
8
7
6
2
1
0
SFORI[2:0]
PON_DAC
PON_ADCL
PON_ADCR
PON_ADC_bias
DACLK_OFF
DACLK_AUTO
−
EN_DEC
−
EN_INT
DACLK_OFF DACLK_AUTO
PON_DAC
SYMBOL
SYMBOL
15
1
7
0
Digital input format. Value to set the digital input format:
000 = I
001 = LSB-justified; 16 bits
010 = LSB-justified; 18 bits
011 = LSB-justified; 20 bits
100 = LSB-justified; 24 bits
101 = MSB-justified
110 = not used; input is default value
111 = not used; input is default value
Power control DAC. If this bit is logic 0, then the DAC is in Power-down mode; if this bit
is logic 1, then the DAC is in power-on mode. This bit is only connected to the DAC input
and is not combined with mute status or other signals.
reserved
Power control ADC left channel. Value to set power on the ADC left channel (see
Table 35).
Power control ADC right channel. Value to set power on the ADC right channel (see
Table 35).
Power control ADC bias. Value to set power on the ADCs (see Table 35).
DAC clock enable. If this bit is logic 0, then the DAC clock is disabled; if this bit is
logic 1, then the DAC clock is enabled.
DAC clock auto function. If this bit is logic 0, then the DAC clock auto function is
disabled; if this bit is logic 1, then the DAC clock auto function is enabled. If the FPLL is
unlocked, the interpolator will be muted and the DAC clock is automatically disabled.
reserved
Decimator and ADC clock enable. If this bit is logic 0, then the clock to decimator and
ADC is disabled; if this bit is logic 1, then the clock to decimator and ADC is running.
reserved
Interpolator clock enable. If this bit is logic 0, then the clock to interpolator and FSDAC
is disabled; if this bit is logic 1, then the clock to the interpolator and FSDAC is running.
14
−
0
6
0
2
S-bus
13
−
0
5
−
0
12
−
0
4
−
0
44
DESCRIPTION
11
0
3
0
−
−
DESCRIPTION
PON_ADCL PON_ADCR PON_ADC_bias
EN_DEC
10
1
2
1
9
1
1
−
0
Preliminary specification
UDA1355H
EN_INT
8
1
0
1