AD1986AJSTZ Analog Devices Inc, AD1986AJSTZ Datasheet - Page 31

• Manufacturer Part Number: AD1986AJSTZ
• Description: IC CODEC HD AUDIO AC'97 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97, HDr

Specifications of AD1986AJSTZ

• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 91
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.97 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register
REF (RO)
(Voltage
References, V
and VREF_OUT
status (read
only))
PR0
PR1
PR2
PR3
PR4
PR5
PR6
EAPD
x
EXTENDED AUDIO ID (REGISTER 0x28)
The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates one
or more of the extended audio features are supported.
Reg
0x28
Table 90.
Register
VRA (RO)
SPDIF (RO)
DRA (RO)
DSA [1:0]
Name
Ext’d Audio ID
REF
ADC
VREF_OUT pin output states controlled by the CVREF, MVREF, and LVREF controls in Register 0x70.
REF
0
1
All ADCs and input selectors’ power down: clearing this bit enables VREF regardless of the state of PR3.
Default: all ADCs and input muxes powered on (0x0).
Front DACs power-down. Also powers down the EQ circuitry. Clearing this bit enables VREF regardless of the state of
PR3. Default: all DACs and EQ powered on (0x0).
Analog mixer power-down. (valid if PR7 = 0).
Default: analog mixer powered on (0x0).
All VREF and VREF_OUT pins power-down. May be used in combination with PR2 or by itself. If all the ADCs and DACs
are not powered down, setting this bit will have no effect on the VREF and will only power down VREF_OUT.
Default: All VREFand VREF_OUT pins powered on (0x0).
AC-Link Interface power-down. The reference and the mixer can be either up or down, but all power-up sequences
must be allowed to run to completion before PR5 and PR4 are both set. In multiple-codec systems, the master codec’s
PR4 bit controls the slave codec. In the slave codec the PR4 bit has no effect except to enable or disable PR5.
Default: AC-link Interface powered on (0x0).
Internal Clocks disabled.
PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down (for example, PR0, PR1, PR4). The reference
and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5
and PR4 are both set. In multiple codec systems, the master codec’s PR5 controls the slave codec. PR5 is effective in the
slave codec if the master's PR5 bit is clear. Default: internal clocks enabled (0x0).
Powers down the headphone amplifiers.
Default: HP amp powered on (0x0).
EAPD
0
1
Reserved.
D15
ID1
Description
Variable rate PCM audio: read only
SPDIF support: read only
Double rate audio: read only
DAC slot assignment (read/write)
DSA [1:0]
00
01
10
11
D14
ID0
D13
x
ADC Status
VREF Status
Voltage References, VREF and VREF_OUT not ready.
Voltage References, VREF, and VREF_OUT up to nominal level.
EAPD Pin Status
Sets the EAPD pin low, enabling an external power amplifier.
Sets the EAPD pin high, shutting the external power amplifier off.
D12
X
Left
3
7
6
10
D11
REV1
Front DAC
D10
REV0
Right
4
8
9
11
Rev. 0 | Page 31 of 56
D9
AMAP
Left
7
6
10
3
D8
LDAC
Setting
= 1
= 1
= 1
Surround DAC
D7
SDAC
Function
Variable rate PCM audio supported
SPDIF transmitter supported (IEC958)
Double rate audio supported for DAC0 L/R
Right
8
9
11
4
D6
CDAC
D5
DSA1
Left
6
10
3
7
D4
DSA0
C/LFE DAC
D3
x
Right
9
11
4
8
Default
Default: 0
SPDF
D2
D1
DRA
Default
Default
AD1986A
D0
VRA
Default
0x0BC7