AD1986AJSTZ Analog Devices Inc, AD1986AJSTZ Datasheet - Page 36

• Manufacturer Part Number: AD1986AJSTZ
• Description: IC CODEC HD AUDIO AC'97 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97, HDr

Specifications of AD1986AJSTZ

• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 91
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.97 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1986A
SPDIF CONTROL (REGISTER 0x3A)
Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe
in the V-case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in
Register 0x2A is 0). This ensures that control and status information start up correctly at the beginning of SPDIF transmission.
Reg
0x3A
Table 98.
Register
PRO
(Professional)
/AUDIO
(Nonaudio)
COPY
(Copyright)
PRE
(Pre-emphasis)
CC [6:0]
(Category Code)
L
(Generation Level)
SPSR
(SPDIF Transmit
Sample Rate)
VCFG
(Validity Force Bit)
V
(Validity)
x
Name
SPDIF
Control
D15
V
Function
Indicates professional use of the audio stream.
PRO
0
1
Indicates that the data is PCM or another format (such as AC3).
/AUDIO
0
1
Allows receivers to make copies of the digital data.
COPY
0
1
Disables filter pre-emphasis.
PRE
0
1
Programmed according to IEC standards, or as appropriate.
Programmed according to IEC standards, or as appropriate.
Chooses between 48.0 kHz and 44.1 kHz S/PDIF transmitter rate.
SPSR
0
1
When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R subframe) to be controlled by the
validity bit (D15) in Register 0x3A (SPDIF control register).
VCFG
0
0
1
1
This bit affects the validity flag, (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to maintain
connection during error or mute conditions. Note that the VCFG bit (0x3A D14) will force the validity flag high (valid) or low
(invalid). See the VCFG bit description.
V
0
1
Reserved.
D14
VCFG
D13
SPSR
State
Consumer use of channel
Professional use of channel
State
Data in PCM format
Data in non-PCM format
State
Copyright asserted
Copyright not asserted
State
Filter pre-emphasis is 50/15 µsec
No pre-emphasis
Transmit Sample Rate
44.1 kHz
48.0 kHz
V
0
1
0
1
State
Each SPDIF subframe (L+R) has Bit 28 set to 1
This tags both samples as invalid
Each SPDIF subframe (L+R) has Bit 28 set to 0 for valid data and 1 for invalid data (error condition)
D12
x
D11
L
D10
CC6
Rev. 0 | Page 36 of 56
D9
CC5
D8
CC4
Validity Bit State
Managed by codec error detection logic
Forced high, indicating subframe data is
invalid
Forced low, indicating subframe data is valid
Forced high, indicating subframe data is
invalid
D7
CC3
D6
CC2
D5
CC1
D4
CC0
D3
PRE
D2
COPY
D1
/AUDIO
Default
Default
Default
Default
Default
Default
Reset Default: 0
Default
Default
Default: 0
D0
PRO
Default
20000x