AD1986AJSTZ Analog Devices Inc, AD1986AJSTZ Datasheet - Page 32

• Manufacturer Part Number: AD1986AJSTZ
• Description: IC CODEC HD AUDIO AC'97 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97, HDr

Specifications of AD1986AJSTZ

• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 91
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.97 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1986A
Register
CDAC (RO)
SDAC (RO)
LDAC (RO)
AMAP (RO)
REV [1:0] (RO)
ID [1:0] (RO)
x
EXT’D AUDIO STAT/CTRL (REGISTER 0x2A)
The extended audio status and control register is a read/write register that provides status and control of the extended audio features.
Reg
0x2A
Table 91.
Register
VRA
(Variable Rate
Audio)
DRA
(Double Rate
Audio)
SPDIF
SPSA [1:0]
(SPDIF Slot
Assignment
Bits:
(Read/Write))
CDAC (RO)
(Center DAC
Status)
LDAC (RO)
(LFE DAC
Status)
SPCV (RO)
Name
Ext’d Audio Stat/Ctrl
Indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed
Function
Enables variable rate audio mode. Enables sample rate registers and SLOTREQ signaling.
VRA
0
1
DRA = 1. Enables double-rate audio mode in which data from PCM L and PCM R in Output Slots 3 and 4 is used in
conjunction with PCM L (n + 1) and PCM R (n + 1) data to provide DAC streams at twice the sample rate designated by the
PCM front sample rate control register. When using the double rate audio, only the front DACs are supported and all other
DACs (surround, center, and LFE) are automatically powered down. The slot that contains the additional data is
determined by the DRSS [1:0] bits (0x20 D [11:10]). Note that DRA can be used without VRA, in which case the converter
rates are forced to 96 kHz if DRA = 1.
DRA
0
1
SPDIF transmitter subsystem enable/disable bit (read/write).
This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed to be set
high, if the SPDIF pin (48) is pulled down at power-up enabling the codec transmitter logic. If the SPDIF pin is floating or
pulled high at power-up, the transmitter logic is disabled and therefore this bit returns a low, indicating that the SPDIF
transmitter is not available. This bit must always be read back, to verify that the SPDIF transmitter is actually enabled.
SPDIF
0
1
AC '97 Revision 2.2 AMAP-compliant default SPDIF slot assignments.
SPSA [1:0]
00
01
10
11
CDAC
0
1
0
1
LDAC
0
1
PCM CENTER DAC: read only
PCM Surround DAC: read only
PCM LFE DAC: read only
Slot DAC mappings: read only
AC97 version: read only
Codec configuration: read only
Reserved
Description
D15
x
D14
x
VRA State
Disabled, sample rate 48 kHz for all ADCs and DACs
Enabled, ADCs and DACs can be set to variable sample rates
DRA State
Disabled, DACs sample at the programmed rate
Enabled, DACs sample at twice (2×) the programmed rate
Disables the S/PDIF transmitter
Enables the S/PDIF transmitter
S/PDIF Slot Assignment
3 and 4
7 and 8
6 and 9
10 and 11
Center DAC not ready
Center DAC section ready to receive data
Surround DAC not ready
Surround DAC section ready to receive data
LFE DAC Status
LFE DAC not ready
LFE DAC section ready to receive data
Function
Center DAC Status
PRK
D13
D12
PRJ
D11
PRI
D10
SPCV
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D9
x
D8
LDAC
Setting
= 10
= 00
= 1
= 1
= 1
= 1
D7
SDAC
Function
PCM center DAC supported
CM Surround DACs supported
PCM LFE DAC supported
Codec ID based slot/DAC mappings
Codec is AC ’97, Revision 2.3-compliant
Primary AC ‘97
Default: 0
D6
CDAC
D5
SPSA1
D4
SPSA0
D3
x
D2
SPDIF
D1
DRA
Default
Default
Default
Default
Default
Default
D0
VRA
Default
0x0xx0