AD1986AJSTZ Analog Devices Inc, AD1986AJSTZ Datasheet - Page 45

• Manufacturer Part Number: AD1986AJSTZ
• Description: IC CODEC HD AUDIO AC'97 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97, HDr

Specifications of AD1986AJSTZ

• Data Interface: Serial
• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 91
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.97 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADVANCED JACK SENSE (REGISTER 0x78)
All register bits are read/write except for JSxST bits, which are read only. Important: Refer to Table 116 to understand how
JACK_SENSE_A and JACK_SENSE_B codec pins translate to JS7…JS2.
Reg
0x78
Table 107.
Register
JS [7:2] INT
JS [7:4] ST (RO)
JS [3:2] MD
JS [4–7]
Interrupt
Mode Select
x
MISC CONTROL BITS 3 (REGISTER 0x7A)
Reg
0x7A
Table 108.
Register
MMIX
GPO
Name
Misc Control
Bits 3
Name
Advanced
Jack Sense
Function
Used in conjunction with the OMS [2:0] (0x74 D10:08), MS (0x20 D08), and 2CMIC (0x76 D06) bits to mix the microphone
selector left/right channels. If the MMIX bit is set, the 2CMIC and MS bits are ignored.
MMIX
0
1
GPO
0
1
Function
JS [7:4] INT
0
1
This bit always reports the logic state of JS7 through JS4 detection logic.
JS [7:4] ST
0
1
This bit selects the operation mode for JS2 and JS3.
JS [3:2] MD
0
1
This bit selects the audio interrupt implementation path (for JS4 to 7). This bit does not generate an interrupt, rather it
steers the path of the generated interrupt.
JS4 to 7
0
1
Reserved
Indicates that JSx has generated an interrupt. Remains set until the software services JSx interrupt; that is, JSx ISR should
clear this bit by writing a 0 to it.
Interrupts are generated by valid state changes of JSx.
Interrupt to the system is actually an OR combination of this bit and JS7 JS0 INT.
Interrupt implementation path is selected by the INTS bit (Register 0x74).
It is also possible to generate a software system interrupt by writing a 1 to this bit.
D15
JSINVB HPSEL1 HPSEL0 LOSEL JSINVA LVREF 2 LVREF1 LVREF 0 x
D15
JS7
ST
D14
D14
JS7
INT
Function
Microphone
channels are not
mixed
The left/right channels from the microphone selector are mixed
Sets the state of the GPO pin
Function
GPO pin is at logic
low (DV
GPO pin is at logic
high (DV
D13
Read
JSx logic is not interrupted
Sx logic interrupted
Jack State
No jack present
Jack detected
Interrupt Mode
Jack Sense Mode—jack sense state requires software polling
Interrupt Mode—jack sense events will generate interrupts
Interrupt Mode—JS4 to 7
Bit 0 Slot 12 (modem interrupt)
Slot 6 valid bit (MIC ADC interrupt)
D13
JS6
ST
SS
DD
)
)
D12
D12
JS6
INT
D11
D11
JS5
ST
Default
Default
Default
D10
JS5
INT
D10
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D9
JS4
ST
D9
D8
JS4
INT
D8
D7
JS4-
7H
Write
Clears JSx interrupt
Generates a software interrupt
D7
D6
x
D6
x
D5
JS3
MD
D5
x
D4
JS2
MD
D4
LOHPEN GPO
D3
JS3
ST
D3
D2
JS2
ST
D2
MMIX x
D1
JS3
INT
D1
D0
JS2
INT
D0
x
AD1986A
Default
Default
Default
Default
Default: 0
Default
0x0000
Default
0xxxxx