LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 121

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Chapter 9 MII Data Interface
SMSC LAN9303/LAN9303i
9.1
9.1.1
9.1.2
9.1.2.1
9.1.2.2
9.1.2.3
The MII Data Path is used to connect the Switch Engine port to the external MII pins, to emulate an
RMII/MII PHY, and to select between PHY and MAC modes.
Port 0 MII MAC Mode
When operating in MII MAC mode, the Switch Fabric MAC output signals are routed directly to the
device’s MII output pins (P0_OUTD[3:0] and P0_OUTDV). The Switch Fabric MAC inputs are sourced
from the MII input pins (P0_IND[3:0], P0_INDV, P0_INER, P0_COL, P0_CRS, P0_OUTCLK, and
P0_INCLK). MII MAC mode can operate at up to 200Mbps.
Port 0 MII PHY Mode
When operating in MII PHY mode, the MII Data Path supplies the RX and TX clocks, creates the CRS
and COL signals and optionally loops back the MII or Switch Engine’s transmissions. It also provides
the collision test function for the external MII pins or Switch Engine. MII PHY mode can operate at up
to 200Mbps (Turbo mode).
The MII pins P0_INCLK, P0_OUTCLK, P0_COL, and P0_CRS, which are inputs when in MII MAC
mode, are outputs when in MII PHY mode. When in MII PHY mode, if the
the
three-stated, the pull-ups and pull-downs are disabled and the MII data path input pins are ignored
(disabled into the non-active state and powered down). Note that setting the
does not cause isolation of the MII management pins and does not affect MII MAC mode.
Turbo Operation
Turbo (200Mbps) operation is facilitated in MII PHY mode via the
PHY Special Control/Status Register
changes the data rate of the MII PHY from 100Mbps to 200Mbps. The
(VPHY_SPEED_SEL_LSB)
toggles between 10 and 200 Mbps operation when
Clock Drive Strength
When operating at 200Mbps (Turbo mode), the drive strength of P0_INCLK and P0_OUTCLK pins is
selected based on the setting of the
Control/Status Register
16ma. When operating at 10 or 100Mbps, the drive strength is fixed at 12ma.
Signal Quality Error (SQE) Heartbeat Test
The SQE_HEARTBEAT signal, observable on the P0_COL pin, is generated in 10Mbit half duplex
mode in response to a transmission from the external MAC. At 0.6uS to 1.6uS (1.0uS nominal)
following the de-assertion of P0_INDV, SQE_HEARTBEAT is set active for 0.5uS to 1.5uS (5 to 15 bit
times) (1.0uS nominal). This test is disabled via the
Control/Status Register
Port 0 MII Data Path
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
(VPHY_SPECIAL_CONTROL_STATUS).
(VPHY_SPECIAL_CONTROL_STATUS). A low selects 12ma, a high selects
bit of the
DATASHEET
RMII/Turbo MII Clock Strength
(VPHY_SPECIAL_CONTROL_STATUS). When set, this bit
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
121
Turbo MII Enable
SQEOFF
is set, MII data path output pins are
Turbo MII Enable
bit of the
is set.
bit of the
Isolate (VPHY_ISO)
Isolate (VPHY_ISO)
Virtual PHY Special
Revision 1.4 (07-07-10)
Speed Select LSB
Virtual PHY Special
bit of the
Virtual
bit of
bit