LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 58

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Revision 1.4 (07-07-10)
5.2.3
5.2.4
5.2.5
5.2.6
In order for a Port 1 or Port 2 interrupt event to trigger the external IRQ interrupt pin, the desired PHY
interrupt event must be enabled in the corresponding
(PHY_INTERRUPT_MASK_x), the
Event (PHY_INT2)
be enabled via the
additional details on the Ethernet PHY interrupts, refer to
page
GPIO Interrupts
Each GPIO[5:0] is provided with its own interrupt. The top-level
Interrupt Status Register (INT_STS)
General Purpose I/O Interrupt Status and Enable Register
Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)
and status of each GPIO[5:0] interrupt.
In order for a GPIO interrupt event to trigger the external IRQ interrupt pin, the desired GPIO interrupt
must be enabled in the
(GPIO_INT_STS_EN), the
(INT_EN)
Interrupt Configuration Register
Section 12.2.1, "GPIO Interrupts," on page
General Purpose Timer Interrupt
A
Interrupt Enable Register
Configuration Register (GPT_CFG)
(GPT_INT)
In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT
must be enabled via the
Configuration Register
Enable Register (INT_EN)
bit of the
Timer, refer to
Software Interrupt
A general purpose software interrupt is provided in the top level
and
Register (INT_STS)
Enable Register (INT_EN)
interrupt, and is designed for general software usage.
Device Ready Interrupt
A device ready interrupt is provided in the top-level
Enable Register
indicates that the device is ready to be accessed after a power-up or reset condition. Writing a 1 to
this bit in the
In order for a device ready interrupt event to trigger the external IRQ interrupt pin, the
Enable (READY_EN)
be enabled via the
GP Timer (GPT_INT)
Auto-Negotiation LP Acknowledge
Parallel Detection Fault
Auto-Negotiation Page Received
Interrupt Enable Register
100.
Interrupt Configuration Register
must be set, and IRQ output must be enabled via the
bit of the
Interrupt Status Register (INT_STS)
Section 11.1, "General Purpose Timer," on page
(INT_EN). The
bits of the
IRQ Enable (IRQ_EN)
IRQ Enable (IRQ_EN)
is generated when the
Interrupt Status Register (INT_STS)
bit of the
(GPT_CFG), the
General Purpose Timer Enable (TIMER_EN)
interrupt is provided in the top-level
must be set, and IRQ output must be enabled via the
GPIO Interrupt Event Enable (GPIO_EN)
is set. This interrupt provides an easy way for software to generate an
(INT_EN). This interrupt is issued when the
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
General Purpose I/O Interrupt Stat us and Enable Regist er
Interrupt Enable Register (INT_EN)
(INT_EN). The
Interrupt Enable Register (INT_EN)
Device Ready (READY)
(IRQ_CFG). For additional details on the GPIO interrupts, refer to
Port 1 PHY Interrupt Event (PHY_INT1)
DATASHEET
wraps past zero to FFFFh, and is cleared when the
provides indication that a GPIO interrupt event occurred in the
GP Timer Interrupt Enable (GPT_INT_EN)
(IRQ_CFG). For additional details on the General Purpose
bit of the
58
bit of the
Software Interrupt Enable (SW_INT_EN)
132.
Software Interrupt (SW_INT)
will clear it.
Interrupt Status Register (INT_STS)
Interrupt Configuration Register
Interrupt Configuration Register
bit of the
is written with 1.
Interrupt Status Register (INT_STS)
Port x PHY Interrupt Mask Register
Section 7.2.8.1, "PHY Interrupts," on
GPIO Interrupt Event (GPIO)
(GPIO_INT_STS_EN). The
131.
Interrupt Status Register (INT_STS)
Interrupt Status Register (INT_STS)
must be set, and IRQ output must
must be set, and IRQ output must
bit of the
IRQ Enable (IRQ_EN)
bit of the
provides enabling/disabling
and/or
bit of the
General Purpose Timer
Interrupt Enable Register
SMSC LAN9303/LAN9303i
General Purpose Timer
IRQ Enable (IRQ_EN)
Port 2 PHY Interrupt
bit of the
bit of the
(IRQ_CFG).
(IRQ_CFG). For
Interrupt Status
Device Ready
and
GP Timer
Datasheet
bit of the
bit of the
General
Interrupt
Interrupt
Interrupt
and