LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 45

• Manufacturer Part Number: LAN9303-ABZJ
• Description: IC ETHER SW 3PORT 16BIT 56QFN
• Manufacturer: SMSC

Specifications of LAN9303-ABZJ

• Controller Type: Ethernet Switch Controller
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 190mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Switches
• Standard Supported: Yes
• Data Rate: 10 Mbps/100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 0.19 A (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1095 - EVALUATION BOARD FOR LAN9303
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1082

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
4.2.3.2
4.2.3.3
4.2.4
In addition to the methods above, the Port 2 PHY is automatically reset after returning from a PHY
power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset
any of the PHY registers. Refer to
additional information.
Port 2 PHY reset completion can be determined by polling the
the
Control Register (PHY_BASIC_CONTROL_x)
clear approximately 110uS after the Port 2 PHY reset occurrence.
Note: When using the
Refer to
Port 1 PHY Reset
A Port 1 PHY reset is performed by setting the
Register (RESET_CTL)
(PHY_BASIC_CONTROL_x). Upon completion of the Port 1 PHY reset, the
(PHY1_RST)
are affected by this reset.
In addition to the methods above, the Port 1 PHY is automatically reset after returning from a PHY
power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset
any of the PHY registers. Refer to
additional information.
Port 1 PHY reset completion can be determined by polling the
the
Control Register (PHY_BASIC_CONTROL_x)
clear approximately 110uS after the Port 1 PHY reset occurrence.
Note: When using the
Refer to
Virtual PHY Reset
A Virtual PHY reset is performed by setting the
Control Register (RESET_CTL)
(VPHY_BASIC_CTRL). No other modules of the device are affected by this reset.
Virtual PHY reset completion can be determined by polling the
the
Control Register (VPHY_BASIC_CTRL)
approximately 1uS after the Virtual PHY reset occurrence.
Refer to
resets.
Configuration Straps
Configuration straps allow various features of the device to be automatically configured to user defined
values. Configuration straps can be organized into two main categories: hard-straps and soft-straps.
Both hard-straps and soft-straps are latched upon Power-On Reset (POR) or pin reset (nRST). The
primary difference between these strap types is that soft-strap default values can be overridden by the
EEPROM Loader, while hard-straps cannot.
Configuration straps which have a corresponding external pin include internal resistors in order to
prevent the signal from floating when unconnected. If a particular configuration strap is connected to
Reset Control Register (RESET_CTL)
Reset Control Register (RESET_CTL)
Reset Control Register (RESET_CTL)
NASR are not reset.
NASR are not reset.
Section 7.2.10, "PHY Resets," on page 101
Section 7.2.10, "PHY Resets," on page 101
Section 7.3.3, "Virtual PHY Resets," on page 104
and
Reset (PHY_RST)
or the
Reset (PHY_RST)
Reset (PHY_RST)
Reset (PHY_RST)
or
DATASHEET
Reset (VPHY_RST)
bits are automatically cleared. No other modules of the device
Section 7.2.9, "PHY Power-Down Modes," on page 100
Section 7.2.9, "PHY Power-Down Modes," on page 100
until it clears. Under normal conditions, these bits will clear
or the
or the
45
or the
bit to reset the Port 2 PHY, register bits designated as
bit to reset the Port 1 PHY, register bits designated as
Port 1 PHY Reset (PHY1_RST)
until it clears. Under normal conditions, these bits will
until it clears. Under normal conditions, these bits will
Reset (PHY_RST)
Reset (PHY_RST)
bit in the (x=1)
Virtual PHY Reset (VPHY_RST)
Reset (VPHY_RST)
for additional information on Port 2 PHY resets.
for additional information on Port 1 PHY resets.
in the
for additional information on Virtual PHY
Virtual PHY Reset (VPHY_RST)
Port 2 PHY Reset (PHY2_RST)
Port 1 PHY Reset (PHY1_RST)
Virtual PHY Basic Control Register
Port x PHY Basic Control Register
bit in the (x=2)
bit in the (x=1)
bit in the
bit of the
Revision 1.4 (07-07-10)
Port 1 PHY Reset
Virtual PHY Basic
Port x PHY Basic
Port x PHY Basic
bit of the
Reset Control
Reset
bit in
bit in
bit in
for
for