LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 140
![IC ETHER SW 3PORT 16BIT 56QFN](/photos/29/2/290201/lan9303_sml.jpg)
LAN9303-ABZJ
Manufacturer Part Number
LAN9303-ABZJ
Description
IC ETHER SW 3PORT 16BIT 56QFN
Manufacturer
SMSC
Specifications of LAN9303-ABZJ
Controller Type
Ethernet Switch Controller
Interface
SMBus (2-Wire/I²C)
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
190mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-QFN
Product
Ethernet Switches
Standard Supported
Yes
Data Rate
10 Mbps/100 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
0.19 A (Typ)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
For Use With
638-1095 - EVALUATION BOARD FOR LAN9303
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1082
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9303-ABZJ
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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Revision 1.4 (07-07-10)
13.2.1
13.2.1.1
31:24
23:15
BITS
11:9
7:5
14
13
12
8
Interrupt De-assertion Interval (INT_DEAS)
This field determines the Interrupt Request De-assertion Interval in multiples
of 10 microseconds.
Setting this field to zero causes the device to disable the INT_DEAS Interval,
reset the interval counter and issue any pending interrupts. If a new, non-
zero value is written to this field, any subsequent interrupts will obey the new
setting.
RESERVED
Interrupt De-assertion Interval Clear (INT_DEAS_CLR)
Writing a 1 to this register clears the de-assertion counter in the Interrupt
Controller, thus causing a new de-assertion interval to begin (regardless of
whether or not the Interrupt Controller is currently in an active de-assertion
interval).
0: Normal operation
1: Clear de-assertion counter
Interrupt De-assertion Status (INT_DEAS_STS)
When set, this bit indicates that interrupts are currently in a de-assertion
interval, and will not be sent to the IRQ pin. When this bit is clear, interrupts
are not currently in a de-assertion interval, and will be sent to the IRQ pin.
0: No interrupts in de-assertion interval
1: Interrupts in de-assertion interval
Master Interrupt (IRQ_INT)
This read-only bit indicates the state of the internal IRQ line, regardless of
the setting of the IRQ_EN bit, or the state of the interrupt de-assertion
function. When this bit is set, one of the enabled interrupts is currently
active.
0: No enabled interrupts active
1: One or more enabled interrupts active
RESERVED
IRQ Enable (IRQ_EN)
This bit controls the final interrupt output to the IRQ pin. When clear, the IRQ
output is disabled and permanently de-asserted. This bit has no effect on
any internal interrupt status bits.
0: Disable output on IRQ pin
1: Enable output on IRQ pin
RESERVED
Interrupts
This section details the interrupt related System CSR’s. These registers control, configure, and monitor
the IRQ interrupt output pin and the various interrupt sources. For more information on interrupts, refer
to
Interrupt Configuration Register (IRQ_CFG)
This read/write register configures and indicates the state of the IRQ signal.
Chapter 5, "System Interrupts," on page
Offset:
054h
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
DATASHEET
140
55.
Size:
32 bits
TYPE
R/W
R/W
R/W
SMSC LAN9303/LAN9303i
RO
RO
RO
RO
RO
SC
SC
DEFAULT
00h
Datasheet
0h
0b
0b
0b
-
-
-
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