LAN9303-ABZJ SMSC, LAN9303-ABZJ Datasheet - Page 75

IC ETHER SW 3PORT 16BIT 56QFN

LAN9303-ABZJ

Manufacturer Part Number
LAN9303-ABZJ
Description
IC ETHER SW 3PORT 16BIT 56QFN
Manufacturer
SMSC
Datasheets

Specifications of LAN9303-ABZJ

Controller Type
Ethernet Switch Controller
Interface
SMBus (2-Wire/I²C)
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
190mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-QFN
Product
Ethernet Switches
Standard Supported
Yes
Data Rate
10 Mbps/100 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
0.19 A (Typ)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
For Use With
638-1095 - EVALUATION BOARD FOR LAN9303
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1082

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9303-ABZJ
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
SMSC LAN9303/LAN9303i
6.4.6
01 - Blocking
01 - Listening
10 - Learning
00 - Forwarding
Port State
Ingress Flow Metering and Coloring
Hardware ingress rate limiting is supported by metering packet streams and marking packets as either
Green, Yellow, or Red according to three traffic parameters: Committed Information Rate (CIR),
Committed Burst Size (CBS), and Excess Burst Size (EBS). A packet is marked Green if it does not
exceed the CBS, Yellow if it exceeds to CBS but not the EBS, or Red otherwise.
Ingress flow metering and coloring is enabled via the
Ingress Rate Configuration Register
packet is classified into a stream. Streams are defined as per port (3 streams), per priority (8 streams),
or per port & priority (24 streams) as selected via the
Rate Configuration Register
setting. All streams share common CBS and EBS settings. CIR, CBS, and EBS are programmed via
the
Ingress Rate Write Data Register
Each stream is metered according to RFC 2697. At the rate set by the CIR, two token buckets are
credited per stream. First, the Committed Burst bucket is incremented up to the maximum set by the
CBS. Once the Committed Burst bucket is full, the Excess Burst bucket is incremented up to the
maximum set by the EBS. The CIR rate is specified in time per byte. The value programmed is in
Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD)
Received packets on the port are
discarded unless overridden.
Transmissions to the port are blocked
unless overridden.
Learning on the port is disabled.
Received packets on the port are
discarded unless overridden.
Transmissions to the port are blocked
unless overridden.
Learning on the port is disabled.
Received packets on the port are
discarded unless overridden.
Transmissions to the port are blocked
unless overridden.
Learning on the port is enabled.
Received packets on the port are
forwarded normally.
Transmissions to the port are sent
normally.
Learning on the port is enabled.
Hardware Action
Table 6.2 Spanning Tree States (continued)
(SWE_INGRSS_RATE_CFG). Each stream can have a different CIR
(SWE_INGRSS_RATE_WR_DATA).
DATASHEET
(SWE_INGRSS_RATE_CFG). Once enabled, each incoming
75
The MAC Address Table should be programmed
with entries that the host CPU needs to receive
(e.g. the BPDU address). The static and override
bits should be set.
The host CPU may send packets to the port in this
state. Only packets with STP override will be
transmitted.
Note:
The MAC Address Table should be programmed
with entries that the host CPU needs to receive
(e.g. the BPDU address). The static and override
bits should be set.
The host CPU may send packets to the port in this
state. Only packets with STP override will be
transmitted.
The MAC Address Table should be programmed
with entries that the host CPU needs to receive
(e.g. the BPDU address). The static and override
bits should be set.
The host CPU may send packets to the port in this
state. Only packets with STP override will be
transmitted.
The MAC Address Table should be programmed
with entries that the host CPU needs to receive
(e.g. the BPDU address). The static and override
bits should be set.
The host CPU may send packets to the port in this
state.
Ingress Rate Enable
Rate Mode
There is no hardware distinction between
the Blocking and Listening states.
Software Action
bits in the
bit in the
Switch Engine Ingress
Revision 1.4 (07-07-10)
and
Switch Engine
Switch Engine

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