TDA8025HN/C1,551 NXP Semiconductors, TDA8025HN/C1,551 Datasheet - Page 13
![IC SMART CARD INTERFACE 32-HVQFN](/photos/6/51/65170/568-32-hvqfn_sml.jpg)
TDA8025HN/C1,551
Manufacturer Part Number
TDA8025HN/C1,551
Description
IC SMART CARD INTERFACE 32-HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.TDA8025HNC1518.pdf
(38 pages)
Specifications of TDA8025HN/C1,551
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Controller Type
Smart Card Interface
Interface
Analog
Voltage - Supply
1.2V, 1.8V, 3V
Current - Supply
65mA
Operating Temperature
-25°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 25 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935286389551
NXP Semiconductors
TDA8025_1
Product data sheet
8.4 Input and output circuits
8.5 Inactive mode
When pins I/O and I/OUC are driven HIGH using an 11 k resistor between pins I/O and
V
referenced to V
The first side on which a falling edge occurs becomes the master. An anti-latch circuit
disables falling edge detection on the other line, making it the slave. After a time delay
t
master-side. When the master returns logic 1, the PMOS transistor on the slave side is
turned on during the time delay (t
to their idle states.
The active pull-up feature ensures fast LOW-to-HIGH transitions making the TDA8025
capable of delivering more than 1 mA, up to an output voltage of 0.9 V
80 pF. At the end of the active pull-up pulse, the output voltage is dependent on the
internal pull-up resistor value and load current. The current sent to and received from the
card’s I/O lines is internally limited to 15 mA at a maximum frequency of 1 MHz.
After a power-on reset, the circuit enters the inactive mode, ensuring only the minimum
number of circuits are active while the TDA8025 waits for the microcontroller to start a
session. The inactive mode conditions are as follows:
d(edge)
Fig 7.
CC
•
•
•
•
•
all card contacts are inactive. The impedance between the contacts and GND is
approximately 200 .
pins I/OUC, AUX1UC and AUX2UC are high-impedance using the 11 k pull-up
resistor connected to V
the voltage generators and crystal oscillator are stopped
the voltage supervisor is active
the internal oscillator runs in low frequency mode
and/or between pins I/OUC and V
I
, the NMOS transistor on the slave-side is turned on. It then sends logic 0 to the
OH
(A)
I/O
Output voltage and current on pins I/O, AUX1 and AUX2 as a function of time
during LOW-to-HIGH transitions
8
6
4
2
0
0
CC
and pin I/OUC to V
I
OH
Rev. 01 — 6 April 2009
20
I/O
DD(INTF)
pu
). After this sequence, both the master and slave return
40
DD(INTF)
DD(INTF)
, thus allowing operation at V
, both lines enter the idle state. Pin I/O is
60
80
V I/O
t (ns)
CC
TDA8025
© NXP B.V. 2009. All rights reserved.
001aai964
IC card interface
, at a load of
CC
100
4
V I/O
3
2
1
0
V
(V)
DD(INTF)
13 of 38
.