TDA8025HN/C1,551 NXP Semiconductors, TDA8025HN/C1,551 Datasheet - Page 29
![IC SMART CARD INTERFACE 32-HVQFN](/photos/6/51/65170/568-32-hvqfn_sml.jpg)
TDA8025HN/C1,551
Manufacturer Part Number
TDA8025HN/C1,551
Description
IC SMART CARD INTERFACE 32-HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.TDA8025HNC1518.pdf
(38 pages)
Specifications of TDA8025HN/C1,551
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Controller Type
Smart Card Interface
Interface
Analog
Voltage - Supply
1.2V, 1.8V, 3V
Current - Supply
65mA
Operating Temperature
-25°C ~ 85°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 25 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935286389551
NXP Semiconductors
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Pin OFFN is an NMOS drain, using an internal pull-up resistor to V
Table 9.
Table 10.
[1]
[2]
[3]
[4]
TDA8025_1
Product data sheet
Symbol
I
I
T
Symbol
t
t
t
t
CC
IO
act
deact
d
deb
sd
To enable the microcontroller to provide the required maximum voltage input level on XTAL1, V
V
the limits of XTAL1.
To meet these specifications, V
and one of 220 nF with an ESR of < 100 m .
Using the internal pull-up resistor to V
Using the internal pull-up resistor to V
The transition time and the duty factor definitions are shown in
Pins PRESN and CMDVCCN are active LOW. Pins RSTIN and PRES are active HIGH; see
CLKDIV2; see
If PRESN or PRES is true, the card is considered to be present. A debouncing feature of 4.5 ms typical is built-in.
Pin PRES has an integrated current source to pin GND, pin PRES to V
the two inputs is true.
See
See
See
See
DD(INTREGD)
Figure 8 on page
Figure 10 on page
Figure 12 on page
Figure 15 on page
Protection characteristics
Timing characteristics
Parameter
supply current
input/output current
shutdown temperature
+ 0.3 V. See
Parameter
activation time
deactivation time
delay time
debounce time
Table 5 on page 19
15.
16.
18.
21.
Section 8.1 on page 7
CC
should be decoupled to pin CGND using two low ESR, ceramic multilayer capacitors one of 470 nF
for pins VCC_SEL1 and VCC_SEL2.
CC
DD(INTF)
Conditions
total sequence with the crystal oscillator
external clock
total sequence
CLK sent to a card with the crystal oscillator
CLK sent to card using an external clock
on pins PRES and PRESN
.
t
t
t
t
d(start)
d(end)
d(start)
d(end)
.
for specific limitations on the maximum V
= t5
= t5
Conditions
shutdown current on
pin V
pin V
pin CLK
pin RST
pins I/O, AUX1 and
AUX2
= t3
= t3
Rev. 01 — 6 April 2009
CC
CC
Figure 16 on page
DD(INTREGD)
DD(INTREGD)
.
30; = t1/(t1 + t2).
; the card is considered as present if at least one of
Min
95
135
-
70
20
15
DD(INTF)
Table 4 on page 12
[1]
[2]
[3]
[1]
[1]
[2]
[2]
[4]
DD(INTF)
Typ
135
175
-
-
-
150
Min
35
35
35
35
160
35
160
3.2
voltage and
must not exceed
Typ
-
-
80
-
-
-
-
4.5
Table 8 on page 23
TDA8025
for pins CLKDIV1 and
Max
185
225
+70
+20
+15
-
© NXP B.V. 2009. All rights reserved.
IC card interface
Max
3000
240
100
3000
3090
150
240
12
Unit
mA
mA
mA
mA
mA
29 of 38
C
Unit
ms
s
s
s
s
s
s
s
for