ISP1583BS ST-Ericsson Inc, ISP1583BS Datasheet - Page 19

• Manufacturer Part Number: ISP1583BS
• Description: IC USB CTRL HI-SPEED 64HVQFN
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1583BS

• Controller Type: USB Peripheral Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
ISP1583_7
Product data sheet
8.13.1 Interrupt output pin
8.13 Interrupt
The Interrupt Configuration register of the ISP1583 controls the behavior of the INT output
pin. The polarity and signaling mode of the INT pin can be programmed by setting bits
INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); see
GLINTENA of the Mode register (R/W: 0Ch) is used to enable pin INT; see
Default settings after reset are active LOW and level mode. When pulse mode is selected,
a pulse of 60 ns is generated when the OR-ed combination of all interrupt bits changes
from logic 0 to logic 1.
Figure 5
Each of the indicated USB and DMA events is logged in a status bit of the Interrupt
register and the DMA Interrupt Reason register, respectively. Corresponding bits in the
Interrupt Enable register and the DMA Interrupt Enable register determine whether an
event will generate an interrupt.
Interrupts can be masked globally by means of bit GLINTENA of the Mode register.
Field CDBGMOD[1:0] of the Interrupt Configuration register controls the generation of INT
signals for the control pipe. Field DDBGMODIN[1:0] of the Interrupt Configuration register
controls the generation of INT signals for the IN pipe. Field DDBGMODOUT[1:0] of the
Interrupt Configuration register controls the generation of INT signals for the OUT pipe;
see
Table
shows the relationship between interrupt events and pin INT.
29.
Rev. 07 — 22 September 2008
Hi-Speed USB peripheral controller
© NXP B.V. 2008. All rights reserved.
ISP1583
Table
Table
25.
28. Bit
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