ISP1583BS ST-Ericsson Inc, ISP1583BS Datasheet - Page 52
![no-image](/images/manufacturer_photos/0/6/627/st-ericsson_inc_sml.jpg)
ISP1583BS
Manufacturer Part Number
ISP1583BS
Description
IC USB CTRL HI-SPEED 64HVQFN
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1583BSUM.pdf
(100 pages)
Specifications of ISP1583BS
Controller Type
USB Peripheral Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1583BS
Manufacturer:
IDT
Quantity:
1 200
Company:
Part Number:
ISP1583BS
Manufacturer:
PHILPS
Quantity:
1 288
Part Number:
ISP1583BS
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
ISP1583BSUM
Manufacturer:
MICRON
Quantity:
2 000
Company:
Part Number:
ISP1583BSUM
Manufacturer:
ST-ERICS
Quantity:
829
Part Number:
ISP1583BSUM
Manufacturer:
STE
Quantity:
20 000
NXP Semiconductors
ISP1583_7
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
XFER_CNT
DIS_
R/W
7
0
0
Table 57.
[1]
Bit
15 to 14
13
12 to 11
10 to 8
7
6 to 4
3 to 2
1
0
The DREQ pin will be driven only after performing a write access to the DMA Configuration register (that is,
after configuring the DMA Configuration register).
6
-
-
-
Symbol
-
ATA_MODE
DMA_MODE
[1:0]
PIO_MODE
[2:0]
DIS_XFER_
CNT
-
MODE[1:0]
-
WIDTH
DMA Configuration register: bit description
[2]
reserved
Rev. 07 — 22 September 2008
5
-
-
-
Description
reserved
ATA Mode: Mode selection of the DMA core.
0 — Configures the DMA core for non-ATA mode. Used when issuing
DMA commands 00h and 01h.
1 — Configures the DMA core for ATA or MDMA mode. Used when
issuing DMA commands 02h to 07h, 0Ah and 0Ch; also used when
directly accessing Task File registers.
DMA Mode: These bits affect the timing for MDMA mode.
00 — MDMA mode 0: ATA(PI) compatible timing
01 — MDMA mode 1: ATA(PI) compatible timing
10 — MDMA mode 2: ATA(PI) compatible timing
11 — MDMA mode 3: enables the DMA Strobe Timing register (see
Table 78
MDMA mode
PIO Mode: These bits affect the PIO timing.
000 to 100 — PIO mode 0 to 4: ATA(PI) compatible timing
101 to 111 — reserved
Disable Transfer Count: Logic 1 disables the DMA Transfer Counter
(see
slave mode; in master mode the counter is always enabled.
reserved
Mode: These bits only affect GDMA (slave) and MDMA (master)
handshake signals.
00 — DIOR (master) or DIOW (slave): strobes data from the DMA bus
into the ISP1583; DIOW (master) or DIOR (slave): puts data from the
ISP1583 on the DMA bus.
01 — DIOR (master) or DACK (slave): strobes data from the DMA bus
into the ISP1583; DACK (master) or DIOR (slave): puts data from the
ISP1583 on the DMA bus.
10 — DACK (master and slave): strobes data from the DMA bus into
the ISP1583 and also puts data from the ISP1583 on the DMA bus.
11 — reserved
reserved
Width: This bit selects the DMA bus width for GDMA (slave) and
MDMA (master).
0 — 8-bit data bus
1 — 16-bit data bus
Table
and
4
-
-
-
54). The transfer counter can be disabled only in GDMA
[1]
Table
79) for non-standard strobe durations; only used in
R/W
3
0
0
MODE[1:0]
Hi-Speed USB peripheral controller
R/W
2
0
0
reserved
© NXP B.V. 2008. All rights reserved.
1
-
-
-
ISP1583
WIDTH
R/W
51 of 99
1
1
0