ISP1583BS ST-Ericsson Inc, ISP1583BS Datasheet - Page 55
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ISP1583BS
Manufacturer Part Number
ISP1583BS
Description
IC USB CTRL HI-SPEED 64HVQFN
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1583BSUM.pdf
(100 pages)
Specifications of ISP1583BS
Controller Type
USB Peripheral Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISP1583BS
Manufacturer:
IDT
Quantity:
1 200
Company:
Part Number:
ISP1583BS
Manufacturer:
PHILPS
Quantity:
1 288
Part Number:
ISP1583BS
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
ISP1583BSUM
Manufacturer:
MICRON
Quantity:
2 000
Company:
Part Number:
ISP1583BSUM
Manufacturer:
ST-ERICS
Quantity:
829
Part Number:
ISP1583BSUM
Manufacturer:
STE
Quantity:
20 000
NXP Semiconductors
Table 62.
CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = LOW, BUS_CONF/DA0 = LOW.
Table 63.
CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = LOW, BUS_CONF/DA0 = HIGH.
Table 64.
CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = HIGH, BUS_CONF/DA0 = LOW.
Table 65.
CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = HIGH, BUS_CONF/DA0 = HIGH.
Table 66.
CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = LOW, BUS_CONF/DA0 = LOW.
ISP1583_7
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Task File 1F0 register (address: 40h): bit allocation
Task File 1F1 register (address: 48h): bit allocation
Task File 1F2 register (address: 49h): bit allocation
Task File 1F3 register (address: 4Ah): bit allocation
Task File 1F4 register (address: 4Bh): bit allocation
R/W
R/W
R/W
R/W
R/W
7
0
0
7
0
0
7
0
0
7
0
0
7
0
0
In 8-bit bus mode, 16-bit Task File register 1F0 requires two consecutive write/read
accesses before the proper PIO write/read is generated on the IDE interface. The first
byte is always the lower byte (LSByte). Other Task File registers can directly be accessed.
Writing to Task File registers can be done in any order, except for the Task File register
1F7, which must be written last.
R/W
R/W
R/W
R/W
R/W
6
0
0
6
0
0
6
0
0
6
0
0
6
0
0
cylinder low/LBA[15:8] (ATA) or cylinder low (ATAPI)
sector number/LBA[7:0] (ATA), reserved (ATAPI)
R/W
R/W
R/W
sector count (ATA) or interrupt reason (ATAPI)
R/W
R/W
5
0
0
5
0
0
5
0
0
5
0
0
5
0
0
Rev. 07 — 22 September 2008
error/feature (ATA or ATAPI)
data (ATA or ATAPI)
R/W
R/W
R/W
R/W
R/W
4
0
0
4
0
0
4
0
0
4
0
0
4
0
0
R/W
R/W
R/W
R/W
R/W
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
Hi-Speed USB peripheral controller
R/W
R/W
R/W
R/W
R/W
2
0
0
2
0
0
2
0
0
2
0
0
2
0
0
R/W
R/W
R/W
R/W
R/W
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1583
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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