IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 105

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

Table 41: Various Operation Modes in Receive Path for Reference
IDT82V2108
4.1.2
ation modes can be set in the transmit path. In each operation mode, the
configurations in Table 41 and Table 42 are illustrated for reference.
Operation
Slave RSCK Ref-
Master Fractional
Signaling Mode
Receive Clock
Slave External
Receive Clock
Master Full E1
Receive Clock
Receive Clock
Receive Multi-
erence Mode
plexed Mode
E1 Mode
Five operation modes can be set in the receive path and four oper-
Mode
VARIOUS OPERATION MODES CONFIGURATION
20H - 3FH (RPLC
indirect registers)
Register
05CH
001H
00EH
010H
012H
001H
00EH
010H
012H
010H
012H
010H
012H
001H
081H
101H
181H
201H
281H
301H
381H
010H
090H
190H
210H
290H
310H
390H
011H
011H
011H
011H
110H
1
Value (from Bit7 to Bit0)
00000000
00001000
00100001
00100000
00000001
01000000
00001000
00100001
00100000
00000001
00001001
00000000
00000001
10001001
00000000
00000001
01000000
01001000
01001000
01001000
01001000
00000011
01011000
01011000
01011000
01011000
00111011
00111011
00111011
00111011
00111011
00111011
00111011
00111011
In the Receive Clock Slave RSCK Reference mode. RSCK is 8 KHZ.
The output on the RSFSn pin is determined by the ROHM, BRXSMFP, BRCMFP and ALTIFP.
In the Receive Clock Slave mode. The FE and DE are both 0. The receive backplane rate is
2.048 Mbit/s.
RSCFS is used.
Enable the normal operation of the RSDn pin.
In the Receive Clock Slave External Signaling mode.
The output on the RSFSn pin is determined by the ROHM, BRXSMFP, BRCMFP and ALTIFP.
In the Receive Clock Slave mode. The FE and DE are both 0. The receive backplane rate is
2.048 Mbit/s.
RSCFS is used.
Enable the normal operation of the RSDn and RSSIGn pins.
In the Receive Clock Master Full E1 Mode. The FE is logic 1 and the DE is logic 0.
RSCFS is un-used.
Enable the normal operation of the RSDn pin.
In the Receive Clock Master Nx64K Mode. The FE is logic 1 and the DE is logic 0.
RSCFS is un-used.
Enable the normal operation of the RSDn pin.
Enable the Receive Payload Control.
The code in the DTRK[7:0] replaces the data output on the RSDn pin in the corresponding
channel.
Multiplex the data stream of these four framers to the multiplexed bus 1.
Multiplex the data stream of these four framers to the multiplexed bus 2.
In Receive Multiplexed mode. The receive backplane rate is 8.192Mbit/s. The FE
is logic 1 and the DE is logic 1.
95
Description
2
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009