IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 192

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
E1 RHDLC #1, #2, #3 Data (04BH, 0CBH, 14BH, 1CBH, 24BH, 2CBH, 34BH, 3CBH)
E1-00AH).
RD[7:0]:
E1 RHDLC #1, #2, #3 Primary Address Match (04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH)
E1-00AH).
PA[7:0]:
E1 RHDLC #1, #2, #3 Secondary Address Match (04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH)
E1-00AH).
SA[7:0]:
Programming Information
Bit Name
Bit Name
Bit Name
Default
Default
Default
Bit No.
Bit No.
Bit No.
Type
Type
Type
Selection of the RHDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6,
This register represents the bytes read from the FIFO. This register should not be accessed at a rate greater than 1/15 of the XCK rate.
The RD[0] corresponds to the first bit of the serial received data from the FIFO.
Selection of the RHDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6,
These bits stipulate the primary address pattern.
PA[0] stores the first bit of the serial data.
Selection of the RHDLC block (#1, #2, or #3) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6,
These bits stipulate the secondary address pattern.
SA[0] stores the first bit of the serial data.
RD[7]
PA[7]
SA[7]
R/W
R/W
R
X
7
7
1
7
1
RD[6]
SA[6]
PA[6]
R/W
R/W
R
6
X
6
1
6
1
RD[5]
SA[5]
PA[5]
R/W
R/W
R
X
5
5
1
5
1
RD[4]
PA[4]
SA[4]
R/W
R/W
R
X
4
4
1
4
1
182
RD[3]
SA[3]
PA[3]
R/W
R/W
R
X
3
3
1
3
1
RD[2]
SA[2]
PA[2]
R/W
R/W
R
2
X
2
1
2
1
T1 / E1 / J1 OCTAL FRAMER
RD[1]
PA[1]
SA[1]
R/W
R/W
R
X
1
1
1
1
1
March 5, 2009
RD[0]
PA[0]
SA[0]
R/W
R/W
R
X
0
0
1
0
1