IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 65

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
3.12
assigned to any of the 8 framers at one time. The PRGD, together with
the Receive / Transmit Payload Control blocks, is used to test the data
stream.
3.12.1
the eight framers can be linked to the pattern generator or detector by
the PRGDSEL[2:0] (b7~5, E1-00CH). The pattern can be inserted in
either the transmit or receive direction, and detected in the opposite
direction. The direction is determined by the RXPATGEN (b2, E1-00CH).
The pattern can be generated and detected in unframed or framed
mode. The selection is made by the UNF_GEN (b1, E1-00CH) and
UNF_DET (b0, E1-00CH) respectively. In unframed mode, all 32 time
slots are replaced or extracted and the specification in the TEST (b7,
E1-RPLC-indirect registers - 20~3FH or b3, E1-TPLC-indirect registers -
20~3FH) in Receive / Transmit Payload Control blocks is ignored. In
3.12.1.2
repetitive or pseudo-random pattern, as chosen by the PS (b4, E1-
070H). Before being compared, the data can be inverted by setting the
RINV (b2, E1-070H). The extracted data is then compared with a 48-bit
fixed window loaded with the pattern. This process goes on until the
data coincides with the pattern. When they are synchronized, it is indi-
cated by the SYNCV (b4, E1-071H). Bit errors in the synchronized data
stream are indicated in the BEI (b2, E1-071H). When there are more
than 10-bit errors in the fixed 48-bit window, the extracted data is out of
synchronization. Automatic search for the re-synch will be done with the
AUTOSYNC (b1, E1-070H) configured, or manual search will be done
when there is a transition from low to high on the MANSYNC (b0, E1-
070H). A manual search is recommended to execute to ensure the
Functional Description
The PRBS Generator/Detector is shared by eight framers. It can be
The PRBS Generator/Detector is a global control block. Any one of
The extracted data from the assigned direction is compared with a
PRBS GENERATOR / DETECTOR (PRGD)
E1 MODE
Pattern Detector
D
SET
CLR
TAP[0]
Q
Q
D
Figure 36. PRBS Pattern Generator
SET
CLR
TAP[1]
Q
Q
D
55
CLR
SET
TAP[2]
framed mode, the time slot is specified by the TEST (b7, E1-RPLC-indi-
rect registers - 20~3FH or b3, E1-TPLC-indirect registers - 20~3FH).
3.12.1.1
070H) is located in the PI[31:0] (b7~0, E1-078H & b7~0, E1-079H &
b7~0, E1-07AH & b7~0, E1-07BH). However, the length of the valid data
in the PI[31:0] is determined by the PL[4:0] (b4~0, E1-072H). If the
repetitive pattern is chosen, the valid PI[X:0] (‘X’ is equal to one number
of the 31 to 1) reflect its content directly. If the pseudo-random pattern is
chosen, the valid PI[X:0] are its initial value and the feedback tap posi-
tion (refer to Figure 36) is determined by the PT[4:0] (b4~0, E1-073H). A
single bit error will be inserted by setting the EVENT (b3, E1-074H) to
‘1’, or continuous bit errors will be inserted at a bit error rate determined
by the EIR[2:0] (b2~0, E1-074H). Before replacing the data in the
assigned direction, the pattern can be inverted by setting the TINV (b3,
E1-070H).
PRGD operates correctly when there is any setting change of the PRGD
registers or the detector data source changes.
E1-07CH & b7~0, E1-07DH & b7~0, E1-07EH & b7~0, E1-07FH) can
contain the received pattern, the total error count or the total number of
received bits. They update when the defined intervals are initiated. The
intervals equal 1 second when the AUTOUPDATE (b0, E1-000H) is set
in the corresponding framer. They can also be updated by writing to any
of the PD[31:0] (b7~0, E1-07CH & b7~0, E1-07DH & b7~0, E1-07EH &
b7~0, E1-07FH), or to the E1 Chip ID / Global PMON Update register
(E1-009H). The update will be indicated by the XFERI (b1, E1-071H). If
they are not read in the defined intervals, the PD[31:0] (b7~0, E1-07CH
& b7~0, E1-07DH & b7~0, E1-07EH & b7~0, E1-07FH) will be overwrit-
ten with new data. The overwritten condition is indicated by the OVR
(b0, E1-071H).
Q
Q
The repetitive or pseudo-random pattern chosen by the PS (b4, E1-
Selected by the PDR[1:0] (b7~6, E1-070H), the PD[31:0] (b7~0,
Pattern Generator
TAP[31]
D
T1 / E1 / J1 OCTAL FRAMER
SET
CLR
Q
Q
March 5, 2009