IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 82

• Manufacturer Part Number: IDT82V2108PXG
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PXG

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V2108PXG

IDT82V2108
3.13.2.1.2
clocked by TSCCKB. The active edge of TSCCKB to sample the pulse
on TSCFS and the data on TSDn and TSSIGn is determined by the
TSCCKBFALL (b3, T1/J1-004H). The TSCCKBFALL (b3, T1/J1-004H)
of the eight framers should be set to the same value to ensure TSCFS
for the eight framers is sampled on the same active edge.
each channel is the first bit to be transmitted.
Functional Description
In this mode (refer to Figure 40), the data on the system interface is
Figure 57 to Figure 59 show the functional timing examples. Bit 1 of
TSCCKB
TSCFS
TSCFS
TSCCKB
TSDn
TSFSn
Figure 57. T1/J1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 1
TSFSn
TSSIGn
TSDn
Transmit Clock Slave External Signaling Mode
Figure 56. T1/J1 Transmit Clock Slave TSFS Enable Mode - Functional Timing Example 3
1
X
(When the TSFSRISE (b5, T1/J1-004) is logic 0:)
(When the TSFSRISE (b5, T1/J1-004) is logic 1:)
1
2
X
2
The TSCCKBFALL (b3, T1/J1-004H) is logic 0. The COFF (b4, T1/J1-015H) is in its default value.
3
X
The CMS (b5, T1/J1-015H) is logic 0. The bankplane rate is 1.544Mbit/s.
3
4
X
4
The CMS (b5, T1/J1-015H) is logic 1. The bankplane clock rate is 4.096Mbit/s.
CH24
CH24
A
5
5
The TSCCKBFALL (b3, T1/J1-004H) is logic 0.
B
6
6
C
7
7
D
8
8
F
X
P
X
1
X
72
X
2
X
Slave mode, the special feature in this mode is that the multi-functional
pin TSFSn/TSSIGn is used as TSSIGn to input the signaling. The signal-
ing on the TSSIGn pin may be configured by the ABXXEN (b4, T1/J1-
005H) to be valid only in the upper two-bit positions of the lower nibble of
each channel (i.e. XXXXABXX) in T1 ESF mode.
X
3
X
Besides all the common functions described in the Transmit Clock
CH1
DUMMY
4
X
X
5
X
X
X
6
X
X
7
F
X
8
1
X
1
2
X
2
T1 / E1 / J1 OCTAL FRAMER
3
CH2
CH1
X
3
4
X
4
5
A
5
6
March 5, 2009