IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 161
IDT82V2108PXG
Manufacturer Part Number
IDT82V2108PXG
Description
IC FRAMER T1/J1/E1 8CH 128-PQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V2108PX8.pdf
(292 pages)
Specifications of IDT82V2108PXG
Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V2108PXG
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Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
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IDT82V2108PXG8
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IDT82V2108
E1 RJAT Configuration (023H, 0A3H, 123H, 1A3H, 223H, 2A3H, 323H, 3A3H)
CENT:
UNDE:
OVRE:
LIMIT:
the read pointer is 1 UI away from the FIFO being empty or full. This limitation of jitter attenuation ensures that no data is lost during high phase shift
conditions.
E1 TJAT Interrupt Status (024H, 0A4H, 124H, 1A4H, 224H, 2A4H, 324H, 3A4H)
OVRI:
UNDI:
Programming Information
Bit Name
Bit Name
Default
Bit No.
Default
Bit No.
Type
The CENT allows the RJAT FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full.
= 0: Disable the self-center. Data is pass through uncorrupted.
= 1: Enable the FIFO to self-center its read pointer when the FIFO is 4 UI away from being empty or full.
A positive transition on this bit will execute a self-center action immediately.
This bit decides whether to generate an interrupt when the RJAT FIFO is under-run.
= 0: No interrupt is generated when the RJAT FIFO is under-run.
= 1: An interrupt on the INT pin is generated when the RJAT FIFO is under-run.
This bit decides whether to generate an interrupt when the RJAT FIFO is overwritten.
= 0: No interrupt is generated when the RJAT FIFO is overwritten.
= 1: An interrupt on the INT pin is generated when the RJAT FIFO is overwritten.
= 0: Disable the limitation of the jitter attenuation.
= 1: Enable the DPLL to limit the jitter attenuation by enabling the FIFO to increase or decrease the frequency of the output smoothed clock when
If data is still attempted to write into the FIFO when the FIFO is already full, the overwritten event will occur.
= 0: The TJAT FIFO is not overwritten.
= 1: The TJAT FIFO is overwritten.
This bit is cleared to ‘0’ when it is read.
If data is still attempted to read from the FIFO when the FIFO is already empty, the under-run event will occur.
= 0: The TJAT FIFO is not under-run.
= 1: The TJAT FIFO is under-run.
This bit is cleared to ‘0’ when it is read.
Type
7
7
Reserved
6
6
5
5
Reserved
CENT
R/W
4
0
4
151
UNDE
R/W
3
3
0
OVRE
R/W
2
2
0
T1 / E1 / J1 OCTAL FRAMER
Reserved
OVRI
R
1
X
1
March 5, 2009
UNDI
LIMIT
R/W
R
0
X
0
1
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