ISP1761ETGE ST-Ericsson Inc, ISP1761ETGE Datasheet - Page 30
ISP1761ETGE
Manufacturer Part Number
ISP1761ETGE
Description
IC USB CTRL HI-SPEED 128TFBGA
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1761BEUM.pdf
(164 pages)
Specifications of ISP1761ETGE
Controller Type
USB Peripheral Controller
Interface
Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
ISP1761ET
ISP1761ET
ISP1761ET
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Manufacturer
Quantity
Price
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NXP Semiconductors
ISP1761_5
Product data sheet
7.8 Overcurrent detection
Table 7
Table 7.
The ISP1761 can implement a digital or analog overcurrent detection scheme. Bit 15 of
the HW Mode Control register can be programmed to select the analog or digital
overcurrent detection. An analog overcurrent detection circuit is integrated on-chip. The
main features of this circuit are self reporting, automatic resetting, low-trip time and low
cost. This circuit offers an easy solution at no extra hardware cost on the board. The port
power will automatically be disabled by the ISP1761 on an overcurrent event occurrence,
by de-asserting the PSWn_N signal without any software intervention.
When using the integrated analog overcurrent detection, the range of the overcurrent
detection voltage for the ISP1761 is 45 mV to 100 mV. Calculation of the external
components must be based on the 45 mV value, with the actual overcurrent detection
threshold usually positioned in the middle of the interval.
Pins
DATA[31:0], A[17:1], TEST, HC_IRQ, DC_IRQ,
HC_DREQ, DC_DREQ, HC_DACK, DC_DACK,
HC_SUSPEND/WAKEUP_N,
DC_SUSPEND/WAKEUP_N
CS_N, RESET_N, RD_N, WR_N
Fig 9.
shows the status of output pins during hybrid mode.
This figure shows the LQFP pinout. For the TFBGA ballout, see
A 4.7 F-to-10 F electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118.
All the electrolytic or tantalum capacitors must be of LOW ESR type (0.2
Hybrid mode
Pin status during hybrid mode
ISP1761BE
Rev. 05 — 13 March 2008
10, 40, 48,
59, 67, 75,
5, 50, 118
104, 115
83, 94,
126
6, 7
85
9
V
V
REG1V8
REG1V8
REG3V3
V
CC(5V0)
CC(I/O)
CC(C_IN)
10 µF
controlled by the CPU
100 nF
3.3 V
V
on
on
off
on
off
CC(I/O)
100 nF
10 µF
100 nF
100 nF
Hi-Speed USB OTG controller
1.65 V to 3.6 V
100 nF
Table
004aaa676
3.3 V to 5 V
V
on
off
X
X
X
100 nF
CC(5V0)
2.
to 2 ).
© NXP B.V. 2008. All rights reserved.
ISP1761
Status
normal
high-Z
undefined
input
undefined
29 of 163
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