ISP1761ETGE ST-Ericsson Inc, ISP1761ETGE Datasheet - Page 36

• Manufacturer Part Number: ISP1761ETGE
• Description: IC USB CTRL HI-SPEED 128TFBGA
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1761ETGE

• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1761ET; ISP1761ET

NXP Semiconductors
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
8.2.1 USBCMD register
8.2 EHCI operational registers
23
15
R
R
R
0
0
7
1
Table 14.
[1]
The USB Command (USBCMD) register indicates the command to be executed by the
serial host controller. Writing to this register causes a command to be executed.
shows the USBCMD register bit allocation.
Bit
31 to 16 -
15 to 8
7 to 4
3
2
1
0
For details on register bit description, refer to
Universal Serial Bus Rev.
22
14
R
R
R
0
0
6
0
Symbol
EECP[7:0]
IST[3:0]
-
ASPC
PFLF
-
HCCPARAMS - Host Controller Capability Parameters register (address 0008h) bit
description
IST[3:0]
21
13
R
R
R
0
0
5
0
Description
reserved; write logic 0
EHCI Extended Capabilities Pointer: Default = implementation
dependent. This optional field indicates the existence of a capabilities list.
Isochronous Scheduling Threshold: Default = implementation
dependent. This field indicates, relative to the current position of the
executing host controller, where software can reliably update the
isochronous schedule.
reserved; write logic 0
Asynchronous Scheduling Park Capability: Default = implementation
dependent. If this bit is set to logic 1, the host controller supports the park
feature for high-speed Transfer Descriptors in the asynchronous schedule.
Programmable Frame List Flag: Default = implementation dependent. If
this bit is cleared, the system software must use a frame list length of 1024
elements with this host controller.
If PFLF is set, the system software can specify and use a smaller frame
list and configure the host through the USBCMD register FLS field.
reserved; write logic 0
Rev. 05 — 13 March 2008
1.0”.
20
12
R
R
R
0
0
4
0
[1]
EECP[7:0]
reserved
Ref. 2 “Enhanced Host Controller Interface Specification for
reserved
19
11
R
R
R
0
0
3
0
ASPC
18
10
R
R
R
0
0
2
1
Hi-Speed USB OTG controller
PFLF
17
R
R
R
0
9
0
1
1
© NXP B.V. 2008. All rights reserved.
ISP1761
reserved
Table 15
35 of 163
16
R
R
R
0
8
0
0
0