SAB82525H-V21 Infineon Technologies, SAB82525H-V21 Datasheet - Page 14
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SAB82525H-V21
Manufacturer Part Number
SAB82525H-V21
Description
IC CONTROLLER SERIAL 44-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.SAB82525N-V21TR.pdf
(126 pages)
Specifications of SAB82525H-V21
Controller Type
Serial Communications Controller (SCC)
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
8mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-BQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
SAB82525H-V21
SAB82525H-V21IN
SAB82525H-V21IN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAB82525H-V21
Manufacturer:
Infineon Technologies
Quantity:
10 000
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P-LCC P-MQFP
Pin Definitions and Functions (cont’d)
Pin No.
36
32
35
33
39
37
Semiconductor Group
41
37
40
38
44
42
Symbol
TxCLK A
TxCLK B
RxCLK A
RxCLK B
DRQRA
DRQRB
Input (I)
I/O
I
Output (O)
O
Function
Transmit Clock (channel A/channel B)
The functions of these pins depend on the programmed
clock mode, provided that the TSS bit in the CCR2 register
is reset. Programmed as inputs (if the TIO bit in CCR2 is
reset), they may supply either
Programmed as outputs (if the TIO bit in CCR2 is set), the
TxCLK pins supply either the
Receive Clock (channel A/channel B)
The functions of these pins also depend on the
programmed clock mode. In each channel, RxCLK may
supply either
DMA Request Receiver (channel A/channel B)
The receiver of the HSCX requests a DMA data transfer by
activating this line.
The DRQRn remains high as long as the receive FIFO
requires data transfers, thus always blocks of data (32, 16,
8 or 4 bytes) are transferred.
DRQRn is deactivated immediately following the falling
edge of the last read cycle.
–
–
–
–
–
–
–
–
the transmit clock for the respective channel (clock
mode 0, 2, 6),
or a transmit strobe signal (clock mode 1).
transmit clock of the respective channel which is
generated either
from the baudrate generator (clock mode 2, 6; TSS bit in
CCR2 set),
or from the DPLL circuit (clock mode 3, 7),
or from the crystal oscillator (clock mode 4)
or a tristate control signal indicating the programmed
transmit time-slot (clock mode 5).
the receive clock (clock mode 0)
or the receive and transmit clock (clock mode 1, 5)
or the clock for the baudrate generator (clock mode 2,
3),
or a crystal connection for the internal
oscillator (clock mode 4,6,7, RxCLK A/B together
with AxCLK A)
14
SAB
SAB
SAF
SAF
82525
82526
82525
82526
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