PIC16F887-E/P Microchip Technology Inc., PIC16F887-E/P Datasheet - Page 143

• Manufacturer Part Number: PIC16F887-E/P
• Description: 40 PIN, 14KB FLASH, 368 RAM, 36 I/O, PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F887-E/P

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 35
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: MSSP or EUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

11.6.4
The PWM mode supports an Auto-Shutdown mode that
will disable the PWM outputs when an external
shutdown event occurs. Auto-Shutdown mode places
the PWM output pins into a predetermined state. This
mode is used to help prevent the PWM from damaging
the application.
The auto-shutdown sources are selected using the
ECCPAS<2:0> bits of the ECCPAS register. A shutdown
event may be generated by:
• A logic ‘0’ on the INT pin
• Comparator C1
• Comparator C2
• Setting the ECCPASE bit in firmware
FIGURE 11-14:
© 2008 Microchip Technology Inc.
From Comparator C2
From Comparator C1
INT
ENHANCED PWM AUTO-
SHUTDOWN MODE
ECCPAS<2:0>
AUTO-SHUTDOWN BLOCK DIAGRAM
111
110
101
100
011
010
001
000
From Data Bus
Write to ECCPASE
PRSEN
PIC16F882/883/884/886/887
R
D
Q
S
A shutdown condition is indicated by the ECCPASE
(Auto-Shutdown Event Status) bit of the ECCPAS
register. If the bit is a ‘0’, the PWM pins are operating
normally. If the bit is a ‘1’, the PWM outputs are in the
shutdown state.
When a shutdown event occurs, two things happen:
The ECCPASE bit is set to ‘1’. The ECCPASE will
remain set until cleared in firmware or an auto-restart
occurs (see Section 11.6.5 “Auto-Restart Mode”).
The enabled PWM pins are asynchronously placed in
their shutdown states. The PWM output pins are
grouped into pairs [P1A/P1C] and [P1B/P1D]. The state
of each pin pair is determined by the PSSAC and
PSSBD bits of the ECCPAS register. Each pin pair may
be placed into one of three states:
• Drive logic ‘1’
• Drive logic ‘0’
• Tri-state (high-impedance)
ECCPASE
PSSAC<1>
PSSAC<1>
PSSBD<1>
PSSBD<1>
PSSAC<0>
P1A_DRV
PSSAC<0>
P1C_DRV
PSSBD<0>
P1B_DRV
PSSBD<0>
P1D_DRV
TRISx
TRISx
TRISx
TRISx
1
0
1
0
1
0
1
0
DS41291E-page 141
P1A
P1C
P1B
P1D