PIC16F887-E/P Microchip Technology Inc., PIC16F887-E/P Datasheet - Page 191

• Manufacturer Part Number: PIC16F887-E/P
• Description: 40 PIN, 14KB FLASH, 368 RAM, 36 I/O, PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F887-E/P

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 35
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: MSSP or EUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.4
The MSSP module in I
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits in
hardware, to determine a free bus (Multi-Master mode).
The MSSP module implements the standard mode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
The MSSP module functions are enabled by setting
MSSP Enable bit SSPEN of the SSPCON register.
FIGURE 13-6:
The MSSP module has these six registers for I
operation:
• MSSP Control Register 1 (SSPCON)
• MSSP Control Register 2 (SSPCON2)
• MSSP STATUS register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
• MSSP Address register (SSPADD)
• MSSP Mask register (SSPMSK)
© 2008 Microchip Technology Inc.
RC3/SCK/SCL
accessible
RC4/
SDI/
SDA
Note:
MSSP I
I/O pins have diode protection to V
Read
Shift
Clock
2
C Operation
MSb
MSSP BLOCK DIAGRAM
(I
SSPMSK Reg
Stop bit Detect
2
SSPADD Reg
2
SSPBUF Reg
Match Detect
SSPSR Reg
C mode, fully implements all
C MODE)
Start and
LSb
DD
Write
and V
(SSPSTAT Reg)
Internal
Data Bus
Set, Reset
S, P bits
Addr Match
SS
.
PIC16F882/883/884/886/887
2
C
The SSPCON register allows control of the I
operation. The SSPM<3:0> mode selection bits
(SSPCON register) allow one of the following I
to be selected:
• I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open drain,
provided these pins are programmed to be inputs by
setting the appropriate TRISC bits.
13.4.1
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
When an address is matched, or the data transfer after
an address match
automatically will generate the Acknowledge (ACK)
pulse and load the SSPBUF register with the received
value currently in the SSPSR register.
If either or both of the following conditions are true, the
MSSP module will not give this ACK pulse:
a)
b)
In this event, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. The BF bit is cleared by reading the SSPBUF
register, while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
MSSP module, are shown in timing parameter #100
and parameter #101.
2
C specification, as well as the requirement of the
Stop bit interrupts enabled
Stop bit interrupts enabled
idle
2
2
2
2
2
2
C Master mode, clock = OSC/4 (SSPADD +1)
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address), with Start and
C Slave mode (10-bit address), with Start and
C firmware controlled master operation, slave is
The buffer full bit BF (SSPCON register) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON register)
was set before the transfer was received.
SLAVE MODE
2
C mode with the SSPEN bit set,
is received,
DS41291E-page 189
the
2
hardware
C modes
2
C