PIC16F887-E/P Microchip Technology Inc., PIC16F887-E/P Datasheet - Page 178

• Manufacturer Part Number: PIC16F887-E/P
• Description: 40 PIN, 14KB FLASH, 368 RAM, 36 I/O, PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F887-E/P

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 35
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 40-pin PDIP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: MSSP or EUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F882/883/884/886/887
12.4.2.3
The operation of the Synchronous Master and Slave
modes is identical (Section 12.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don't care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS41291E-page 176
BAUDCTL ABDOVF
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRG
SPBRGH
TRISC
TXREG
TXSTA
Legend:
never Idle
Name
x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
EUSART Receive Data Register
EUSART Transmit Data Register
TRISC7
BRG15
SPEN
BRG7
CSRC
EUSART Synchronous Slave
Reception
Bit 7
GIE
—
—
TRISC6
BRG14
RCIDL
BRG6
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
TRISC5
BRG13
SREN
BRG5
TXEN
RCIE
RCIF
Bit 5
T0IE
—
TRISC4
BRG12
CREN
SYNC
SCKP
BRG4
INTE
Bit 4
TXIE
TXIF
ADDEN
TRISC3
SENDB
BRG16
BRG11
SSPIE
SSPIF
BRG3
RBIE
Bit 3
CCP1IE
CCP1IF
TRISC2
BRG10
FERR
BRGH
BRG2
12.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
Bit 2
T0IF
—
Set the SYNC and SPEN bits and clear the
CSRC bit.
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
BRG1
BRG9
WUE
Bit 1
INTF
Synchronous Slave Reception Set-
up:
TMR1IE
TMR1IF
TRISC0
ABDEN
RX9D
BRG0
BRG8
TX9D
Bit 0
RBIF
© 2008 Microchip Technology Inc.
01-0 0-00
0000 000x
-000 0000
-000 0000
0000 0000
0000 000x
0000 0000
0000 0000
1111 1111
0000 0000
0000 0010
POR, BOR
Value on
01-0 0-00
0000 000x
-000 0000
-000 0000
0000 0000
0000 000x
0000 0000
0000 0000
1111 1111
0000 0000
0000 0010
Value on
all other
Resets