PIC16F887-E/P Microchip Technology Inc., PIC16F887-E/P Datasheet - Page 37
PIC16F887-E/P
Manufacturer Part Number
PIC16F887-E/P
Description
40 PIN, 14KB FLASH, 368 RAM, 36 I/O, PDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F887-EP.pdf
(328 pages)
Specifications of PIC16F887-E/P
A/d Inputs
14-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Frequency
20 MHz
Input Output
35
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Resistance, Drain To Source On
Bytes
Serial Interface
MSSP or EUSART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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2.2.2.7
The PIR2 register contains the interrupt flag bits, as
shown in Register 2-7.
REGISTER 2-7:
© 2008 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OSFIF
R/W-0
PIR2 Register
OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
EEIF: EE Write Operation Interrupt Flag bit
1 = Write operation completed (must be cleared in software)
0 = Write operation has not completed or has not started
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the MSSP when configured for I
0 = No bus collision has occurred
ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag bit
1 = Wake-up condition has occurred (must be cleared in software)
0 = No Wake-up condition has occurred
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
R/W-0
C2IF
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
W = Writable bit
‘1’ = Bit is set
R/W-0
C1IF
PIC16F882/883/884/886/887
R/W-0
EEIF
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
BCLIF
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
ULPWUIF
R/W-0
software
2
C Master mode
x = Bit is unknown
U-0
should
—
DS41291E-page 35
ensure
CCP2IF
R/W-0
bit 0
the
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